Semiconductor processing techniques
AssigneeApplied Materials, Inc.
InventorJaim Nulman
Life of this patent
Estimating the term…
Abstract
The present invention provides a manufacturing environment (110) for a wafer fab, and an SPC environment (112) for setting control limits and acquiring metrology data of production runs. A computation environment (114) processes the SPC data, which are then analyzed in an analysis environment (116). An MES environment (118) evaluates the analysis and automatically executes a process intervention if the process is outside the control limits. Additionally, the present invention provides for an electrical power management system, a spare parts inventory and scheduling system and a wafer fab efficiency system. These systems employ algorithms (735, 1135 and 1335).
Claims17
An apparatus for electrical power management in IC fabrication including a plurality of processing tools, the apparatus comprising:
- a) a power monitor environment adapted for automatically collecting power usage information regarding each of the plurality of processing tools;
- and
- b) a computation environment adapted for:
- (1) obtaining a first sequence for using the plurality of processing tools,
- (2) incorporating the power usage information in the first sequence,
- (3) determining a first power usage profile for the first sequence and
- (4) developing a second sequence having a power usage profile which is contained within a predetermined range.
An apparatus for electrical power management in IC fabrication including a plurality of processing tools, the apparatus comprising a computation environment adapted for determining a sequence for using the plurality of tools such that a power usage of the IC fabrication is optimized for avoiding tool related power surges.
An apparatus for electrical power management in IC fabrication including a plurality of processing tools, the apparatus comprising a technology adapted for determining a sequence for using the plurality of tools such that the sequence is optimized for obtaining a low circuit breaker rating.
A computer apparatus for electrical power management in an IC fabrication process including a plurality of processing tools, the apparatus comprising one or more technologies for:
- a) identifying the plurality of processing tools;
- b) obtaining a first sequence for using the plurality of processing tools in the IC fabrication;
- c) automatically collecting processing tool information regarding each of the plurality of processing tools, including processing tool electrical power usage;
- d) incorporating the processing tool information in the first sequence;
- e) determining a first power usage profile of the first sequence;
- and
- f) developing a second sequence such that the power usage profile remains within a predetermined range.
An apparatus for electrical power management in IC fabrication including a first wafer fab having a first plurality of processing tools and a second wafer fab having a second plurality of processing tools, the apparatus comprising:
- a) a power monitor environment adapted for automatically collecting power usage information regarding each of the tools of the first plurality of tools and each of the second plurality of tools;
- and
- b) a computation environment adapted for:
- (1) obtaining a first sequence for using each of the tools,
- (2) incorporating the power usage information in the first sequence,
- (3) determining a first power usage profile for the first sequence and
- (4) developing a second sequence having a power usage profile which is contained within a predetermined range.
An apparatus for electrical power management in IC formation having a plurality of processing tools including at least one tool that is not incorporated in a cluster tool, the apparatus comprising:
- a) a power monitor environment adapted for automatically collecting power usage information regarding each of the plurality of processing tools;
- and
- b) a computation environment adapted for:
- (1) obtaining a first sequence for using the plurality of processing tools,
- (2) incorporating the power usage information in the first sequence,
- (3) determining a first power usage profile for the first sequence and
- (4) developing a second sequence having a power usage profile which is contained within a predetermined range.
A memory including a digitally encoded data structure for electrical power management in IC fabrication including a plurality of processing tools, the data structure comprising computer implemented methods for:
- a) identifying the plurality of processing tools;
- b) obtaining a first sequence for using the plurality of processing tools in the IC fabrication;
- c) automatically collecting processing tool information regarding each of the plurality of processing tools, including processing tool electrical power usage;
- d) incorporating the processing tool information in the first sequence;
- e) determining a first power usage profile of the first sequence;
- and
- f) developing a second sequence such that the power usage profile remains within a predetermined range.
A memory including a digitally encoded data structure for electrical power management in IC fabrication, wherein the data structure comprises a computer implemented algorithm including:
- a) defining a process for the IC fabrication;
- b) defining a predetermined power usage profile for the process;
- c) determining a power usage profile for a production run of the process, wherein the profile is an actual usage profile or an expected power usage profile;
- d) analyzing the production run power usage profile to determine whether this profile is within the predetermined power usage profile;
- e) executing the process if the production run power usage profile is within the predetermined power usage profile;
- and
- f) modifying the process if the production run power usage profile is outside the predetermined power usage profile.
Dependencies are inferred from the claim text.