Integrated circuit packaging with tapered striplines of constant impedance
AssigneeInternational Business Machine Corporation
InventorsEdward R. Pillai, Warren D. Dyckman, Deana Cosmadelis
Life of this patent
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Abstract
In a package for integrated circuits, a signal transmission line has a first segment closer to the chip that is bracketed vertically by ground planes at a first vertical distance and a second segment further from the chip that is bracketed vertically by ground planes at a second vertical distance greater than the first distance, with an aperture being formed in the ground planes at the first distance, so that those ground planes do not interfere with the impedance set by the second set of ground planes.
Claims12
A multilayer package for holding at least one integrated circuit chip, having a top surface, a bottom surface;
- a top contact array attached to said top surface and a set of layers of dielectric disposed between said top surface and bottom surface;
- a bottom contact array attached to said bottom surface;
- at least one conductive signal line within said multilayer package connecting a bottom contact to a top contact, said conductive signal line comprising a first horizontal segment of a first width and a second horizontal segment of a second width greater than said first width, in which said first horizontal segment is bracketed vertically by a first set of top and bottom ground planes separated vertically from said first horizontal segment by a first vertical distance and said second horizontal segment is bracketed vertically by a second set of top and bottom ground planes separated vertically from said second horizontal segment by a second vertical distance greater than said first vertical distance, said first and second vertical distances being set to maintain a design impedance.
Dependencies are inferred from the claim text.