Semiconductor memory device and its method of manufacture
AssigneeSamsung Electronics Co., Ltd.
InventorHan-Soo Kim
Life of this patent
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Abstract
A semiconductor memory device comprises a semiconductor substrate having a memory cell region and a periphery circuit region. The memory cell region includes first and second conductivity type wells and an array of memory cell formed on the first and second conductivity type wells. The periphery circuit region comprises a guard ring that is formed at a location next to a second conductivity type well and to surround a side portion of the array of memory cells. The guard ring is formed with a depth different from that of the second conductivity type well.
Claims16
A memory device, comprising:
- a semiconductor substrate;
- an array of memory cells within a memory cell region of the semiconductor substrate;
- first and second conductivity-type wells in the semiconductor substrate including the memory cell region;
- and
- a guard ring in a periphery circuit region of the semiconductor substrate outside the memory cell region;
- the guard ring surrounding a side of the array of memory cells, and
- the guard ring comprising a depth deeper than that of the second conductivity-type wells of the memory cell region, the guard ring being separated from the second conductivity type wells of the memory cell region.
A semiconductor memory device, comprising:
- a semiconductor substrate of a first conductivity type, the semiconductor substrate comprising a memory cell region and a periphery circuit region;
- first and second conductivity type wells in the memory cell region;
- an array of memory cells formed on the first and second conductivity type wells in the memory cell region;
- a first conductivity type well in the periphery circuit region adjacent to the first and second conductivity type wells of the memory cell region;
- and
- a second conductivity type well in the periphery circuit region;
- the second conductivity type well of the periphery circuit region adjacent to the first conductivity type well of the periphery circuit region, surrounding a side portion of the memory cell region and having a depth deeper than that of the second conductivity type well of the memory cell region.
A semiconductor memory device, comprising:
- a semiconductor substrate comprising a memory cell region and a periphery circuit region;
- a first conductivity type well within the memory cell region;
- and
- a guard ring within the periphery circuit region surrounding a side portion of the memory cell region;
- the guard ring comprising a depth deeper than that of the first conductivity type well, the guard ring being separated from the first conductivity type well of the memory cell region.
A semiconductor memory device, comprising:
- a semiconductor substrate of a first conductivity type, the semiconductor substrate comprising a memory cell region and a periphery circuit region;
- first conductivity type wells in the memory cell region and the periphery circuit region;
- and
- a well of second conductivity type in the periphery circuit region to surround a side portion of the memory cell region;
- the well of second conductivity type in the periphery circuit region comprising a depth deeper than that of the first conductivity type well of the memory cell region.
Dependencies are inferred from the claim text.