Sidewall NROM and method of manufacture thereof for non-volatile memory cells
AssigneesAdvanced Micro Devices, Inc., Fujitsu Limited
InventorsRichard M. Fastow, Shane C. Hollmer, Pau-Ling Chen, Michael Van Buskirk, Masaaki Higashitani
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Abstract
An non-volatile read only memory transistor for use in a memory array is disclosed. The non-volatile read only memory transistor features a substantially vertically oriented channel fabricated in a trench formed in the substrate. The channel length is dependent upon the depth of the trench and therefore a dense array of NROM transistors can be formed without adversely affecting the channel length and therefore the operational performance of the transistor.
Claims12
A non-volatile read only memory transistor comprising:
- a channel region having a first end coupled with a source and a second end coupled with a drain;
- a gate comprising a wordline layer formed in a trench without completely filling said trench;
- said source having a first surface located in a first plane and said drain having a second surface located in a second plane, said second plane being oriented substantially parallel to and non-coplanar with said first plane;
- and
- wherein said channel region is located in a third plane, said third plane being oriented substantially perpendicular to and non-coplanar with said first and second planes, and wherein said drain overlaps at least a portion of said source.
An electronic device comprising:
- one or more non-volatile read only memory transistors, said one or more non-volatile read only memory transistors each comprising:
- a channel having a first end comprising a source and a second end comprising a drain;
- a gate comprising a wordline layer formed in a trench without completely filling said trench;
- said source being located in a first plane and said drain located in a second plane, said second plane being oriented substantially parallel to said first plane;
- and
- wherein said channel is located in a third plane, said third plane being oriented substantially perpendicular to said first and second planes, and wherein said drain overlaps at least a portion of said source.
An electronic device comprising:
- a substrate comprising one or more trenches formed in said substrate, each of said one or more trenches having first and second top portions, a bottom portion oriented substantially parallel to said first and second top portions, a first wall extending between said first top portion and said bottom portion substantially perpendicularly to said bottom and said first top portion and a second wall extending substantially perpendicularly from said second top portion to said bottom portion, said first wall being substantially parallel to said second wall;
- a first non-volatile read only memory transistor, comprising:
- a first channel having a first end comprising a first source and a second end comprising a first drain;
- a first gate comprising a wordline layer formed in one of said trenches without completely filling said trench;
- said first drain being located in said first top portion and said first source being located in said bottom portion;
- and
- wherein said first channel is located in said first wall, and wherein said first drain overlaps at least a portion of said first source.
A non-volatile read only memory transistor comprising:
- a substrate having a substantially planar surface and a trench;
- a gate comprising a wordline layer formed in said trench without completely filling said trench;
- a source region fabricated in said substrate;
- a drain region fabricated in said substrate;
- and
- a channel region fabricated in said substrate and extending between and connecting said source region and said drain region;
- and
- wherein said channel region is out of plane of said source region and said drain region, and wherein said drain region overlaps at least a portion of said source region.
Dependencies are inferred from the claim text.