Random access memory cell and method for fabricating same

A semiconductor memory device, comprising:

• an array of memory cells organized into a plurality of rows and columns of memory cells, wherein each row of memory cells is connected to a distinct word line and each column of memory cells is connected to a distinct pair of bit lines;
• address decode circuitry, coupled to the word lines and the bit lines, for receiving an input address and connecting a row of memory cells to the bit lines in response;
• data input-output circuitry, coupled to the bit lines, for providing input data to be written to the array of memory cells and providing output data read from the array of memory cells to circuitry external to the semiconductor memory device;
• and
• control circuitry which charges the bit lines to a low reference voltage level between memory access operations;
• wherein each memory cell comprises:
• a first transistor having a control terminal, a first conduction terminal connected to a reference voltage supply and a second conduction terminal;
• a second transistor having a control terminal connected to the second conduction terminal of the first transistor, a first conduction terminal connected to the reference voltage supply and a second conduction terminal connected to the control terminal of the first transistor;
• a first transmission gate transistor having a control terminal connected to a word line, a first conduction terminal connected to a first bit line of a bit line pair, and a second conduction terminal connected to the second conduction terminal of the first transistor;
• and
• a second transmission gate transistor having a control terminal connected to the word line, a first conduction terminal connected to a second bit line of the bit line pair, and a second conduction terminal connected to the second conduction terminal of the second transistor;
• wherein the first transmission gate transistor has a subthreshold leakage current that maintains the second conduction terminal of the first transistor at a logic level when the first transistor is turned off, the second transmission gate transistor has a subthreshold leakage current that maintains the second conduction terminal of the second transistor at a logic level when the second transistor is turned off, the first and second transistors comprise a first and a second pull-up transistor, respectively, and each memory cell is free of cross-coupled pull-down transistors coupled to the first and second pull-up transistors.

A volatile memory cell, consisting essentially of:

• a first transistor having a control terminal, a first conduction terminal coupled to a reference voltage source and a second conduction terminal;
• a second transistor having a control terminal connected to the second conduction terminal of the first transistor, a first conduction terminal coupled to the reference voltage source and a second conduction terminal connected to the control terminal of the first transistor;
• a first transmission gate transistor having a control terminal, a first conduction terminal capable of being coupled to a first bit line of a bit line pair and a second conduction terminal connected to the second conduction terminal of the first transistor;
• and
• a second transmission gate transistor having a control terminal, a first conduction terminal capable of being coupled to a second bit line of the bit line pair, a second conduction terminal connected to the second conduction terminal of the second transistor, the first transistor and the second transistor comprise a first pull-up transistor and a second pull-up transistor, respectively, the reference voltage source comprises a high reference voltage source, and the volatile memory cell is free of cross-coupled pull-down transistors coupled to the first and second pull-up transistors.

A semiconductor memory device, comprising:

• an array of memory cells organized into a plurality of rows and columns of memory cells, wherein each row of memory cells is connected to a distinct word line and each column of memory cells is connected to a distinct pair of bit lines;
• address decode circuitry, coupled to the word lines and the bit lines, for receiving an input address and connecting a row of memory cells to the bit lines in response;
• data input-output circuitry, coupled to the bit lines, for providing input data to be written to the array of memory cells and providing output data read from the array of memory cells to circuitry external to the semiconductor memory device;
• and
• control circuitry which charges the bit lines to a low reference voltage level between memory access operations;
• wherein at least one memory cell comprises:
• a first transistor having a control terminal, a first conduction terminal connected to a reference voltage supply and a second conduction terminal;
• a second transistor having a control terminal connected to the second conduction terminal of the first transistor, a first conduction terminal connected to the reference voltage supply and a second conduction terminal connected to the control terminal of the first transistor;
• a first transmission gate transistor having a control terminal connected to a word line, a first conduction terminal connected to a first bit line of a bit line pair, and a second conduction terminal connected to the second conduction terminal of the first transistor;
• and
• a second transmission gate transistor having a control terminal connected to the word line, a first conduction terminal connected to a second bit line of the bit line pair, and a second conduction terminal connected to the second conduction terminal of the second transistor;
• wherein the first transmission gate transistor has a subthreshold leakage current that maintains the second conduction terminal of the first transistor at a logic level when the first transistor is turned off, the second transmission gate transistor has a subthreshold leakage current that maintains the second conduction terminal of the second transistor at a logic level when the second transistor is turned off, the first and second transistors comprise a first and a second pull-up transistor, respectively, and the at least one memory cell is free of cross-coupled pull-down transistors coupled to the first and second pull-up transistors.