Multichannel receiver circuit for parallel reception

Abstract

A multichannel receiver circuit is provided, which suppresses effectively crosstalk or interference between the electric signals transmitted in parallel through multiple channels at high speed and which improves the S/N for each channel. The receiver circuit comprises first to n-th sections for forming respectively first to n-th channels, where n is an integer greater than unity. The first to n-th sections receive first to n-th electric input signals to produce first to n-th electric output signals, respectively, where each of the first to n-th output signals having different logic levels according to a corresponding one of the first to n-th input signals. Each of the first to n-th sections includes an output level fixer circuit that produces an output signal. The output signal of the output level fixer circuit having a fixed level that induces no oscillation when a corresponding one of the first to n-th input signals has a level less than a specific reference level. The output signal of the output level fixer circuit has substantially a same waveform as that of a corresponding one of the first to n-th input signals when a corresponding one of the first to a-th input signals has a level equal to or greater than the specific reference level. The level fixer circuit may be formed by a multilevel retainer circuit or a Schmitt trigger circuit.

Dependencies are inferred from the claim text.