Use of a sacrificial layer to facilitate metallization for small features
AssigneeTexas Instruments Incorporated
InventorsJiong-Ping Lu, Changming Jin, David Permana
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Abstract
A method of fabricating a copper interconnect using a sacrificial layer. A SiC layer (106) is formed over the dielectric layer (102). A sacrificial layer (108) is formed over the SiC layer (106). A trench (112) is etched in the sacrificial layer (108), the SiC layer (106) and the dielectric layer (102). A sputter etch of the sacrificial layer (108) is used to create a wider opening at a top of the sacrificial layer (108) than at a top of the dielectric layer (102). A barrier layer (114) and copper seed layer (116) are formed. The trench (112) is then filled with copper (124). CMP is used to remove the excess copper (124) and barrier layer (114) stopping on the SiC (106).
Claims16
A method of fabricating an integrated circuit, comprising the steps of:
- forming a dielectric layer over a semiconductor body;
- forming a polish stop layer over said dielectric layer;
- forming a sacrificial layer over said polish stop layer;
- forming a hole in said sacrificial layer, said polish stop layer and said dielectric layer;
- performing a sputter etch of said sacrificial layer to pull-back a top corner of said sacrificial layer wherein said polish stop layer protects corners of said dielectric layer from said sputter etch;
- forming a barrier layer over said sacrificial layer and in said hole;
- depositing a copper seed layer over said barrier layer;
- and
- depositing copper to fill said hole.
A method of fabricating an integrated circuit, comprising the steps of:
- forming a dielectric layer over a semiconductor body;
- forming a SIC layer over said dielectric layer;
- forming a sacrificial layer over said SiC layer, said sacrificial layer comprising a material with a higher CMP polish rate than the SiC;
- forming a trench in said sacrificial layer, said SIC layer and said dielectric layer;
- performing a sputter etch of said sacrificial layer to create a wider opening at a top of said sacrificial layer than at a top of said dielectric layer, wherein said SiC layer protects corners of said dielectric layers from said sputter etch;
- forming a barrier layer over said sacrificial layer and in said trench;
- depositing a copper seed layer over said barrier layer, wherein said wider opening at the top of the sacrificial layer minimizes an overhang of said copper seed layer;
- and
- depositing copper to fill said trench.
A method of fabricating an integrated circuit, comprising the steps of:
- forming a dielectric layer over a semiconductor body;
- forming a SIC layer over said dielectric layer;
- forming a sacrificial layer over said SIC layer;
- forming a trench in said sacrificial layer, said SiC layer and said dielectric layer;
- performing a sputter etch of said sacrificial layer to create a wider opening at a top of said sacrificial layer than at a top of said dielectric layer, wherein said SiC layer protects corners of said dielectric layers from said sputter etch;
- forming a barrier layer over said sacrificial layer and In said trench;
- depositing a copper seed layer over said barrier layer;
- depositing copper to fill said trench;
- and
- chemically-mechanically polishing said copper and said barrier layer to form a copper interconnect.
Dependencies are inferred from the claim text.