Chip design with power rails under transistors

A method for an integrated circuit with power rails under transistors;

• comprising:
• a) providing a substrate;
• b) forming a first power rail over said substrate;
• c) forming a first insulating layer over said first power rail;
• d) forming a second power rail over said first insulating layer;
• e) forming a second insulating layer over said second power rail;
• and
• f) forming a first epi layer over said second insulating layer;
• g) forming first and second contact holes in said first epi layer;
• said first contact hole exposing said first power rail;
• and said second contact hole exposing said second power rail,
• h) forming first and second liner layers on the sidewalls of said first and second contact holes;
• i) forming a first contact plug in said first contact hole to contact said first power rail;
• and forming a second contact plug in said second contact hole to contact said second power rail;
• j) forming a second epi layer over said first epi layer and said first and second liner layers and said first and second contact plugs;
• k) forming a gate dielectric layer, a gate over said second epi layer;
• l) forming source and drain regions in said second epi layer adjacent to said gate;
• said source and drain regions contact said first and second contact plugs.

A method for an integrated circuit with power rails under transistors;

• comprising:
• a) providing a substrate;
• b) forming a first power rail over said substrate;
• c) forming a first insulating layer over said first power rail;
• d) forming a second power rail over said first insulating layer;
• e) forming a second insulating layer over said second power rail;
• f) forming a first epi layer over said second insulating layer and said substrate;
• g) forming first and second contact holes in said first epi layer;
• said first contact hole exposing said first power rail;
• and said second contact hole exposing said second power rail;
• h) forming first and second liner layers on the sidewalls of said first and second contact holes;
• i) forming a first contact plug in said first contact hole to contact said first power rail;
• and forming a second contact plug in said second contact hole to contact said second power rail;
• j) forming a second epi layer over said first epi layer and said first and second liner layers and said first and second contact plugs;
• k) forming a gate dielectric layer, a gate over said second epi layer;
• l) forming source and drain regions in said second epi layer adjacent to said gate;
• said source and drain regions contact said first and second contact plugs;
• m) forming a dielectric layer over said second epi layer, said source and drain regions, and said gate;
• n) forming contacts to said source and drain regions and said gate;
• o) forming a first conductive layer to contact said contacts.

A method for an integrated circuit with power rails under transistors;

• comprising:
• a) providing a substrate;
• b) forming a first power rail over said substrate;
• (1) said first power rail comprised of W;
• (2) said first power rail has a thickness between 0.3 and 1 μm;
• c) forming a first insulating layer over said first power rail;
• d) forming a second power rail over said first insulating layer;
• (1) said second power rail comprised of W;
• (2) said second power rail has a thickness between 0.3 and 1 μm;
• e) forming a second insulating layer over said second power rail;
• f) forming a first epi layer over said second insulating layer;
• (1) said first epi layer has a thickness between 4 and 20 μm;
• g) forming first and second contact holes in said first epi layer;
• said first contact hole exposing said first power rail;
• and said second contact hole exposing said second power rail;
• (1) said first and second contact holes are formed using an electrochemical etch;
• (2) forming first and second contact holes have a width between 0.3 and 1 μm and a depth between 4 and 20 μm;
• h) forming first and second liner layers on the sidewalls of said first and second contact holes;
• i) forming a first contact plug in said first contact hole to contact said first power rail;
• and forming a second contact plug in said second contact hole to contact said second power rail;
• j) forming a second epi layer over said first epi layer and said first and second liner layers and said first and second contact plugs;
• k) forming a gate dielectric layer, a gate over said second epi layer;
• l) forming source and drain regions in'said second epi layer adjacent to said gate;
• said source and drain regions contact said first and second contact plugs;
• m) forming a dielectric layer over said second epi layer, said source and drain regions, and said gate;
• n) forming contacts to said source and drain regions and said gate;
• and
• o) forming a first conductive layer to contact said contacts.

A method for an integrated circuit with power rails under transistors;

• comprising:
• a) providing a substrate;
• b) forming a first power rail over said substrate;
• c) forming a second power rail over said first power rail;
• said second power rail is insulated from said first power rail;
• d) forming an epi layer over said first power rail and second power rail;
• e) forming contact holes in said epi layer to expose said first and said second power rails:
• f) forming-contact plugs in said contact holes;
• said contact plugs contacting said first and said second power rails;
• g) forming transistors over and/or in said epi layer, said transistors connected to said contact plugs.