Polycide structure and method for forming polycide structure
AssigneeMicron Technology, Inc.
InventorYongjun Jeff Hu
Life of this patent
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Abstract
A polycide structure for use in an integrated circuit comprises a silicon layer; a barrier layer comprising ZSix where x is greater than two and Z is chosen from the group consisting of tungsten, tantalum and molybdenum; and a metal silicide layer, preferably cobalt silicide. The structure is particularly useful in applications requiring high temperature processing. The structure may be used as a gate stack, especially in memory applications such as DRAM. The structure provides thermal stability, thus avoiding agglomeration problems associated with high temperature processing combined with low resistivity.
Claims68
A method of forming a conductive polycide layer, the method comprising the steps of
- forming a first polysilicon layer;
- forming a barrier layer in contact with the first polysilicon layer, the barrier layer comprising ZSix, wherein x is greater than two and Z is chosen from the group consisting of tungsten, tantalum and molybdenum;
- and
- forming a metal silicide layer in contact with the barrier layer, wherein said metal silicide layer is formed of a different metal than said barrier layer.
A method of forming a transistor gate stack in an integrated circuit, the method comprising the steps of
- forming a gate dielectric layer;
- forming a first polysilicon layer in contact with the gate dielectric layer;
- forming a barrier layer in contact with the first polysilicon layer, the barrier layer comprising ZSix, wherein x is greater than two and Z is chosen from the group consisting of tungsten, tantalum and molybdenum;
- and
- forming a metal silicide layer in contact with the barrier layer, wherein said metal silicide layer is formed of a different metal than said barrier layer.
A method of forming an integrated circuit comprising at least one transistor, the method comprising the step of:
- forming source and drain areas in a substrate;
- and forming a gate stack;
- wherein the gate stack forming step comprises:
- forming a gate dielectric layer;
- forming a first polysilicon layer in contact with the gate dielectric layer;
- forming a barrier layer in contact with the first polysilicon layer, the barrier layer comprising ZSix, wherein x is greater than two and Z is chosen from the group consisting of tungsten, tantalum and molybdenum;
- and
- forming a metal silicide layer in contact with the barrier layer, wherein said metal silicide layer is formed of a different metal than said barrier layer.
A method of forming a memory cell, the method comprising the steps of:
- forming at least one capacitor;
- and
- forming at least one transistor;
- wherein the transistor forming step comprises:
- forming source and drain areas in a substrate;
- and
- forming a gate stack;
- wherein the gate stack forming step comprises:
- forming a gate dielectric layer;
- forming a first polysilicon layer in contact with the gate dielectric layer;
- forming a barrier layer in contact with the first polysilicon layer, the barrier layer comprising ZSix, wherein x is greater than two and Z is chosen from the group consisting of tungsten, tantalum and molybdenum;
- and
- forming a metal silicide layer in contact with the barrier layer, wherein said metal silicide layer is formed of a different metal than said barrier layer.
Dependencies are inferred from the claim text.