Process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure

An improved process for forming, in a reactor, a low k carbon-doped silicon oxide dielectric material of an integrated circuit structure on a semiconductor substrate, said low k carbon-doped silicon oxide dielectric material characterized by improved planarity and good gap fill in high aspect ratio regions of said integrated circuits structure which comprises:

• a) forming a base layer of dielectric material on said integrated circuit structure;
• b) etching the upper surface of said base layer with an oxygen plasma;
• c) cooling said etched base layer down to a temperature within about 10° C. of the subsequent deposition temperature;
• d) depositing over said etched base layer of dielectric material, to a thickness not exceeding about 400 μm, a first of a plurality of layers of said low k carbon-doped silicon oxide dielectric material, while maintaining said reactor at a temperature of from about 4° C. to about 15° C., and at a pressure of from about 400 millitorr to about 900 millitorr;
• and
• e) pausing for from at least 20 seconds to about 90 seconds, after forming each of said layers of low k carbon-doped silicon oxide dielectric material and before depositing a further layer of said low k carbon-doped silicon oxide dielectric material;
• and
• f) flowing, during said pausing step, a non-reactive gas over said first layer of low k carbon-doped silicon oxide dielectric material at a flow rate equivalent to from about 8 l/m to about 10 l/m in a 0.5 liter reactor.

An improved process for forming, in a reactor, a low k carbon-doped silicon oxide dielectric material of an integrated circuit structure on a semiconductor substrate, said low k carbon-doped silicon oxide dielectric material characterized by improved planarity and good gap fill in high aspect ratio regions of said integrated circuits structure which comprises:

• a) forming, on said integrated circuit structure, a base layer of a dielectric material comprising silicon, oxygen, and at least about 7 atomic percent nitrogen;
• b) etching the upper surface of said base layer with an oxygen plasma;
• c) cooling said etched base layer down to a temperature within about 10° C. of the subsequent deposition temperature;
• d) depositing over said etched base layer of dielectric material, to a thickness not exceeding about 400 μm, a first of a plurality of layers of said low k carbon-doped silicon oxide dielectric material, by flowing into said reactor a gaseous source of peroxide and a gaseous organo-silane, while maintaining said reactor at a temperature of from about 4° C. to about 15° C., and at a pressure of from about 400 millitorr to about 700 millitorr;
• and
• e) pausing for from at least 20 seconds to about 90 seconds, after forming each of said layers of low k carbon-doped silicon oxide dielectric material and before depositing a further layer of said low k carbon-doped silicon oxide dielectric material;
• and
• f) flowing over said first layer of low k carbon-doped silicon oxide dielectric material, during said pausing step, a non-reactive gas selected from the group consisting of nitrogen, argon, neon, and helium at a flow rate equivalent to from about 8 l/m to about 10 l/m in a 0.5 liter reactor.

An improved process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure characterized by improved planarity and good gap fill in high aspect ratio regions of said integrated circuits structure which comprises:

• a) depositing a plurality of layers of said low k carbon-doped silicon oxide dielectric material on an integrated circuit structure in a reactor, by flowing a mild oxidizing agent and one or more gaseous sources of silicon into said reactor at flow rates equivalent to flow rates into a 0.5 liter reactor of:
• i) from about 0.5 grams/minute to about 1.8 grams per minute of a 60 vol. % aqueous H2O2 solution;
• ii) from about 70 standard cubic centimeters per minute (sccm) to about 120 sccm of methylsilane;
• and
• iii) from 0 to about 40 sccm of silane;
• while maintaining a pressure in said reactor ranging from about 400 millitorr to about 900 millitorr;
• and
• b) pausing after depositing each layer of said low k carbon-doped silicon oxide dielectric material and before depositing a further layer of said low k carbon-doped silicon oxide dielectric material.

An improved process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure characterized by improved planarity and good gap fill in high aspect ratio regions of said integrated circuits structure which comprises:

• a) depositing a plurality of layers of said low k carbon-doped silicon oxide dielectric material on an integrated circuit structure in a reactor;
• b) pausing, for a period of at least about 10 seconds, after depositing each layer of said low k carbon-doped silicon oxide dielectric material;
• and
• c) then flowing a non-reactive gas into said reactor over said previously deposited layer of low k carbon-doped silicon oxide dielectric material at a flow rate equivalent to a flow rate of from about 6 liters/minute (l/m) to about 12 l/m flowing into a 0.5 liter reactor for a period of at least about 15 second before commencing deposition of a further layer of said low k carbon-doped silicon oxide dielectric material.

An improved process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure characterized by improved planarity and good gap fill in high aspect ratio regions of said integrated circuits structure which comprises:

• a) forming, over said integrated circuit structure, a base layer of dielectric material containing at least about 7 atomic percent nitrogen therein;
• b) then etching an upper surface of said base layer;
• c) then depositing a plurality of layers of said low k carbon-doped silicon oxide dielectric material on an integrated circuit structure in a reactor;
• and
• d) pausing after depositing each layer of said low k carbon-doped silicon oxide dielectric material and
• e) cooling said base layer down to a temperature not more than about 10° C. above the deposition temperature before depositing a further layer of said low k carbon-doped silicon oxide dielectric material.