Semiconductor devices utilizing differently composed metal-based in-laid gate electrodes

Abstract

MOS transistor and CMOS devices comprising a plurality of transistors including in-laid, metal-based gate electrodes of different composition are formed by a process comprising: depositing a first blanket layer of a first metal filling openings in an insulative layer at the bottom of which openings gate insulator layer segments of MOS transistor precursor regions formed in a semiconductor substrate are exposed; selectively forming at least one masking layer segment on the first blanket layer overlying selected ones of the MOS transistor precursor regions; depositing a second blanket layer of a second metal or silicon over the thus-formed structure, and effecting alloying or silicidation reaction between contacting portions of the first and second blanket layers overlying other ones of the MOS transistor precursor regions. Unnecessary layers remaining after alloying or silicidation reaction are then removed by performing planarization processing, e.g., by CMP. The invention also includes MOS and CMOS devices comprising differently composed in-laid, metal-based gate electrodes.

Dependencies are inferred from the claim text.