US 6,583,003 B1 · Method of fabricating 1T1R resistive memory array

Abstract

A method is provided for forming a 1T1R resistive memory array. The method of forming a 1T1R resistive memory array structure on a semiconductor substrate comprises forming an array of transistors comprising a polycide/oxide/nitride gate stack with nitride sidewalls, the transistors comprising a source and a drain region adjacent to the gate stack. An insulating layer is deposited and planarized level with the polycide/oxide/nitride gate stack. Bit contact openings are etched to expose the drain region. Bottom electrodes are formed by depositing and planarizing a metal. A resistive memory material is deposited over the bottom electrodes. Top electrodes are formed over the resistive memory material. The 1T1R resistive memory array may be connected to support circuits that are formed on the same substrate as the memory array. The support circuits may share many of the process steps with the formation of the transistors for the memory array.

Claims25

Dependent claims

A method of forming a 1T1R resistive memory array structure on a semiconductor substrate comprising:

a) forming a polycide/oxide/nitride gate stack overlying a gate dielectric on the semiconductor substrate;
b) producing source and drain regions adjacent to the gate stack;
c) performing a salicide process to form a silicide over the exposed source and drain regions;
d) forming nitride sidewalls along the gate stack;
e) depositing and planarizing a silicon oxide insulation layer level with the gate stack;
f) patterning and etching bit contacts that connect to the drain regions;
g) depositing and planarizing a bottom electrode;
h) depositing a layer of resistive memory material;
and
i) forming top electrodes over the resistive memory material.

7 more elements

Dependencies are inferred from the claim text.

Method of fabricating 1T1R resistive memory array

Life of this patent

Method of fabricating 1T1R resistive memory array

Life of this patent

Abstract

Claims25