US 6,583,002 B2 · SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY MEMORY DEVICES, METHODS OF FORMING CAPACITOR CONTAINERS, METHODS OF MAKING ELECTRICAL CONNECTION TO CIRCUIT NODES AND RELATED INTEGRATED CIRCUITRY

Abstract

In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed over the conductive layer to provide conductive structure in both areas. According to one aspect of this implementation, the conductive layer is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another aspect of this implementation, the conductive layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide.

Claims10

Dependent claims

A semiconductor processing method of making an electrical connection to a circuit node comprising:

forming a first electrically conductive material outwardly of and in electrical connection with a circuit node;
forming a second electrically conductive material outwardly of and in electrical connection with the first electrically conductive material;
forming an insulative dielectric layer outwardly of the second electrically conductive material;
etching an opening in the insulative dielectric layer to the second electrically conductive material;
and
etching the second electrically conductive material substantially selective relative to the first electrically conductive material.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

09/884,950Filed 19 Jun 2001 · continuation

Priority

13 Mar 1997

Published

US 2001/0036698 A11 Nov 2001

Granted

24 Jun 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10B 12/033
Making the capacitor or connections thereto: the capacitor extending over the transistor
Y10S 257/906
Active solid-state devices, e.g. transistors, solid-state diodes: dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate
Y10S 257/907
Active solid-state devices, e.g. transistors, solid-state diodes: folded bit line dram configuration
Y10S 257/908
Active solid-state devices, e.g. transistors, solid-state diodes: dram configuration with transistors and capacitors of pairs of cells along a…

Family

Application08/816,621Parent of this division · filed 13 Mar 1997

Application09/087,114Parent of this continuation · filed 29 May 1998

US 2001/0036698 A1Pre-grant publication · published 1 Nov 2001

US 6,261,899 B1Parent of this continuation

Application09/087,114Parent of this division

US 5,998,257 AParent of this division

US 6,583,002 B2This patent

From the US filing history. Foreign family members aren’t listed.

Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry

Life of this patent

Semiconductor processing methods of forming integrated circuitry memory devices, methods of forming capacitor containers, methods of making electrical connection to circuit nodes and related integrated circuitry

Life of this patent

Abstract

Claims10