Process integration of Si1-xGex CMOS with Si1-xGex relaxation after STI formation

A method of forming a CMOS device, comprising:

• preparing a silicon substrate, including forming plural device regions on the substrate;
• epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40% and a thickness of between about 2500 Å to 4000 Å, and which forms a SiGe:silicon interface with the silicon substrate;
• forming a silicon cap layer epitaxially on the SiGe layer;
• depositing a gate oxide layer;
• depositing a first polysilicon layer to a thickness of between about 1000 Å and 3000 Å;
• implanting H+ ions to a depth below the SiGe:silicon interface;
• forming a trench by shallow trench isolation which extends into the substrate;
• annealing the structure at a temperature of between about 700° C. to 900° C. for between about five minutes to sixty minutes, wherein said annealing also provides for liner oxidation of the trench sidewall;
• depositing an oxide layer and a second polysilicon layer, thereby filling the trench;
• planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench;
• and
• completing the CMOS device, including LDD, halo, source/drain ion implantation, gate spacer formation, interlayer dielectric deposition, contact masking and etching, and metalization of electrodes.

A method of forming a CMOS device, comprising:

• preparing a silicon substrate, including forming plural device regions on the substrate and includes an N-well and a P-well in each device region;
• epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40% and a thickness of between about 2500 Å to 4000 Å;
• forming a silicon cap layer epitaxially on the SiGe layer to a thickness of between about 50 Å to 300 Å;
• depositing a gate oxide layer to a thickness of between about 10 Å and 60 Å;
• depositing a first polysilicon layer;
• implanting H+ ions to a depth of between about 2 nm to 100 nm below the SiGe layer at a dose of between about 1×1016cm−2 to 4×1016cm−2, and at an energy of between about 40 keV to 80 keV;
• forming a trench by shallow trench isolation which extends into the substrate;
• annealing the structure at a temperature of between about 700° C. to 900° C. for between about five minutes to sixty minutes;
• depositing an oxide layer and a second polysilicon layer, thereby filling the trench;
• planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench;
• and
• completing the CMOS device.