Method for fabricating a shallow ion implanted microelectronic structure

#1. Field of the Invention

#The present invention relates generally to methods for fabricating ion implanted microelectronic structures, as employed for fabricating microelectronic fabrications. More particularly, the present invention relates to methods for fabricating shallow ion implanted microelectronic structures, as employed for fabricating microelectronic fabrications.

#2. Description of the Related Art

#The objects, features and advantages of the present invention are understood within the context of the Description of the Preferred Embodiment, as set forth below. The Description of the Preferred Embodiment is understood within the context of the accompanying drawings, which form a material part of this disclosure, wherein:

#FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIG. 5 and FIG. 6 show a series of schematic cross-sectional diagrams illustrating the results of progressive stages in forming, in accord with a preferred embodiment of the present invention, a field effect transistor (FET) device within a semiconductor integrated circuit microelectronic fabrication.

#The present invention provides a method for fabricating within a semiconductor integrated circuit microelectronic fabrication a semiconductor device, and in particular a field effect transistor (FET) device, wherein the semiconductor device, and in particular the field effect transistor (FET) device, is fabricated with decreased dimensions and enhanced performance.

#The present invention realizes the foregoing object when fabricating within the semiconductor integrated circuit microelectronic fabrication the field effect transistor (FET) device by: (1) implanting, while masking a pair of source/drain locations within an active region of a semiconductor substrate, a first dose of a first dopant into a patterned gate electrode material layer to form therefrom a gate electrode; and (2) implanting, while not masking the pair of source/drain locations within the active region of the semiconductor substrate, a second dose of a second dopant into the pair of source/drain locations to form a pair of source/drain regions. In particular, by masking the pair of source/drain locations within the active region of the semiconductor substrate when implanting the first dose of the first dopant into the patterned gate electrode material layer to form the gate electrode, the pair of source/drain regions when formed within the pair of source/drain locations may be formed independently and with more controlled ion implantation properties, such as in particular to provide the pair of source/drain regions with a controlled and shallow junction depth.

#While, in accord with the foregoing, the present invention more preferably provides a method for forming within a semiconductor integrated circuit microelectronic fabrication, and with decreased dimensions and enhanced performance, a field effect transistor (FET) device, in a more general sense, the present invention also provides an analogous method for forming an ion implanted topographic microelectronic structure formed over a substrate employed within a microelectronic fabrication while independently forming an ion implanted structure within the substrate adjacent the ion implanted topographic microelectronic structure.