Passivation layer for packaged integrated circuits
AssigneeMicron Technology, Inc.
InventorsTongbi Jiang, Zhiping Yin
Life of this patent
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Abstract
Passivating layers methods for forming the same are provided for packaged integrated circuit devices. In particular, an integrated circuit die is mounted in a plastic leaded chip carrier, and a photosensitive material is then deposited over the surfaces to be passivated. Portions of the photosensitive material are then exposed to UV light, resulting in a crosslinked siloxane network. In this way, a low-temperature photodefinable passivation layer is provided for the package, with characteristics similar to conventional oxides. Advantageously, the photosensitive material can be patterned during the UV exposure, and unexposed portions selectively removed to leave the passivation layer only over desired portions of the package.
Claims22
A process for forming a passivated integrated circuit device, comprising:
- mounting a die onto a surface of a die carrier;
- and
- reacting an organosilane precursor to form a layer of photosensitive material onto surfaces of the die and the die carrier.
A method of packaging an integrated circuit die to form a surface mount device, comprising:
- mounting the die onto a surface of a plastic die carrier;
- and
- depositing a photodefinable layer on the die and the die carrier after mounting the die;
- and
- converting the photodefinable layer to a passivation layer.
A method of packaging an integrated circuit die for surface mounting, the method comprising:
- mounting the die on a die carrier;
- forming plasma polymerized methylsilane (PPMS) onto a back side of the die and die carrier after mounting the die;
- and
- exposing at least a portion of the PPMS to ultraviolet light in the presence of oxygen.
Dependencies are inferred from the claim text.