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US 6,582,990 B2Granted
Wafer level underfill and interconnect process
AssigneeInternational Rectifier Corporation
InventorMartin Standing
Life of this patent
Estimating the term…
Abstract
A chip scale package and a method for its manufacture which include providing sticky interconnects on a surface of a semiconductor die, the interconnects being surrounded by a layer of thermal epoxy.
Claims19
A method for manufacturing a semiconductor device, comprising:
- depositing a passivation layer over a major surface of a semiconductor wafer, said semiconductor wafer including a plurality of identical semiconductor die isolated from one another by streets, each die having a major electrical contact on a major surface thereof;
- creating a plurality of windows in said passivation layer, each window being positioned over and exposing said major electrical contact of a respective die;
- depositing conductive epoxy containing conductive particles in each of said windows to form an interconnect over each of said major electrical contacts;
- forming a layer of thermal epoxy around each of said interconnects;
- and
- dicing said wafer along said streets to form a plurality of semiconductor devices.
3 more elements
A method for attaching a semiconductor die having a major electrical contact on a major surface thereof to a conductive pad, comprising:
- disposing an interconnect on said major electrical contact, said interconnect being comprised of a sticky epoxy containing conductive particles;
- surrounding said interconnect with a layer of thermal epoxy;
- sticking said interconnect to said conductive pad;
- heating said interconnect to a reflow temperature to form a connection between said interconnect and said conductive pad;
- and
- further heating said thermal epoxy to a curing temperature, said curing temperature being above said reflow temperature.
3 more elements
Dependencies are inferred from the claim text.