Composition for wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof

A manufacturing method of a TFT substrate for a display, comprising:

• depositing a metal layer made of Al or Al alloy on a substrate;
• depositing a MoW alloy layer including tungsten of 0.01 atm % to 20 atm %, the rest of molybdenum and inevitable impurity, on the metal layer and the substrate;
• forming a gate line, a gate electrode connected to the gate line, and a gate pad connected to the gate line by patterning the MoW alloy layer and etching the metal layer using an etchant;
• depositing a gate insulating layer;
• forming an un-doped amorphous silicon layer and a doped amorphous silicon layer;
• forming a data pattern including a data line, a source and a drain electrode, and a data pad connected to the data line;
• etching the doped amorphous silicon layer using the data pattern as an etch mask;
• depositing a passivation layer;
• patterning the passivation layer along with the gate insulating layer to expose portions of the gate pad, the data pad and the drain electrode;
• depositing a transparent conductive layer;
• and
• etching the transparent conductive layer to form a gate conductive layer connected to the gate pad and a pixel electrode connected to the drain electrode,
• wherein the metal layer comprises an aluminum and a transition metal or a rare earth metal less than 5%,
• wherein the etchant is CH3COOH/HNO3/H3PO4/H2O having HNO3 of the concentration of 8-14%,
• wherein the data pattern comprises either a single layer of one selected from the group consisting of Cr, Mo or MoW alloy including tungsten, the rest of molybdenum and inevitable impurity, or a layer having a dual-layered structure of two selected from the group consisting of Cr, Mo or MoW alloy including tungsten, the rest of molybdenum and inevitable impurity, and
• wherein the patterning step comprises;
• forming a photoresist pattern on the passivation layer, the photoresist pattern having openings at the positions corresponding to the gate pad, the data pad and the drain electrode,
• exposing the data pad and the drain electrode under the condition of etch selectivity rate of the photoresist pattern to the insulating layer and the passivation layer in range of 1:1 to 1:1.5;
• and
• exposing the gate pad under the condition of etch rate of the gate insulating layer and the passivation layer larger than 15 times than the etch rate of the data pattern.

A manufacturing method of a TFT substrate for a display, comprising:

• depositing a metal layer made of Al or Al alloy on a substrate;
• depositing a MoW alloy layer including tungsten of 0.01 atm % to 20 atm %, the rest of molybdenum and inevitable impurity, on the metal layer and the substrate;
• forming a gate line, a gate electrode connected to the gate line, and a gate pad connected to the gate line by patterning the MoW alloy layer and etching the metal layer using an etchant;
• depositing a gate insulating layer;
• forming an un-doped amorphous silicon layer and a doped amorphous silicon layer;
• forming a data pattern including a data line, a source and a drain electrode, and a data pad connected to the data line;
• etching the doped amorphous silicon layer using the data pattern as an etch mask;
• depositing a passivation layer;
• patterning the passivation layer along with the gate insulating layer to expose portions of the gate pad, the data pad and the drain electrode;
• depositing a transparent conductive layer;
• and
• etching the transparent conductive layer to form a gate conductive layer connected to the gate pad and a pixel electrode connected to the drain electrode,
• wherein the metal layer comprises an aluminum and a transition metal or a rare earth metal less than 5%,
• wherein the etchant is CH3COOH/HNO3/H3PO4/H2O having HNO3 of the concentration of 8-14%,
• wherein the data pattern comprises either a single layer of one selected from the group consisting of Cr, Mo or MoW alloy including tungsten, the rest of molybdenum and inevitable impurity, or a layer having a dual-layered structure of two selected from the group consisting of Cr, Mo or MoW alloy including tungsten, the rest of molybdenum and inevitable impurity, and
• wherein the patterning step comprises;
• forming a photoresist pattern on the passivation layer, the photoresist pattern having openings at the positions corresponding to the gate pad, the data pad and the drain electrode,
• exposing the data pad and the drain electrode;
• forming a polymer layer on the substrate by reacting CF4 and either H2 or HCl in plasma;
• and
• exposing the gate pad under the condition of etch rate of the gate insulating layer and the passivation layer larger than 15 times than the etch rate of the data pattern.

A manufacturing method of a TFT substrate for a display, comprising:

• depositing a metal layer made of Al or Al alloy on a substrate;
• depositing a MoW alloy layer including tungsten of 0.01 atm % to 20 atm %, the rest of molybdenum and inevitable impurity, on the metal layer and the substrate;
• forming a gate line, a gate electrode connected to the gate line, and a gate pad connected to the gate line by patterning the MoW alloy layer and etching the metal layer using an etchant;
• depositing a gate insulating layer;
• forming an un-doped amorphous silicon layer and a doped amorphous silicon layer;
• forming a data pattern including a data line, a source and a drain electrode, and a data pad connected to the data line;
• etching the doped amorphous silicon layer using the data pattern as an etch mask;
• depositing a passivation layer;
• patterning the passivation layer along with the gate insulating layer to expose portions of the gate pad, the data pad and the drain electrode;
• depositing a transparent conductive layer;
• and
• etching the transparent conductive layer to form a gate conductive layer connected to the gate pad and a pixel electrode connected to the drain electrode,
• wherein the metal layer comprises an aluminum and a transition metal or a rare earth metal less than 5%,
• wherein the etchant is CH3COOH/HNO3/H3PO4/H2O having HNO3 of the concentration of 8-14%,
• wherein the data pattern comprises either a single layer of one selected from the group consisting of Cr, Mo or MoW alloy including tungsten, the rest of molybdenum and inevitable impurity, or a layer having a dual-layered structure of two selected from the group consisting of Cr, Mo or MoW alloy including tungsten, the rest of molybdenum and inevitable impurity, and
• wherein the patterning step comprises;
• forming a photoresist pattern on the passivation layer, the photoresist pattern having openings at the positions corresponding to the gate pad, the data pad and the drain electrode,
• exposing the data pad, the drain electrode and the gate pad by using the photoresist pattern as an etch mask and by using CF4+O2.

A manufacturing method of a TFT substrate for display comprises steps:

• depositing a MoW alloy layer including tungsten of 0.01 atm % to 20 atm %, the rest of molybdenum and inevitable impurity on a substrate;
• forming a gate line, a gate electrode connected to the gate line, and a gate pad connected to the gate line by patterning the MoW alloy layer using an etchant and using a first mask;
• depositing a gate insulating layer, an undoped amorphous silicon layer, a doped amorphous silicon layer, and a metal layer in sequence on the substrate;
• etching sequentially the metal layer, the doped amorphous silicon layer and the undoped amorphous silicon layer using a second mask;
• forming a pixel electrode having opening on the metal layer using a third mask;
• forming a data line, a source and a drain electrode, and a contact layer by etching the metal layer and the doped amorphous silicon layer using the pixel electrode as a mask;
• depositing a passivation layer;
• and
• etching the passivation along with the gate insulating layer on the gate pad using a fourth mask.

A method of manufacturing a thin film transistor panel for display, comprising:

• forming a gate line having a dual-layered structure and tapered edges at an angle of 20˜70 degrees on a substrate;
• depositing a gate insulating layer;
• forming an un-doped amorphous silicon layer and a doped amorphous silicon layer;
• forming a data line, a source electrode and a drain electrode;
• forming a passivation layer;
• depositing a transparent conductive layer on the passivation layer;
• and
• etching the transparent conductive layer to form a gate conductive layer connected to an end portion of the gate line, a data conductive layer connected to an end portion of the data line, and a pixel electrode connected to the drain electrode.