Structure and method for fabrication of a leadless chip carrier with embedded antenna

Abstract

A substrate has a top surface for receiving a semiconductor die. An antenna is patterned on the bottom surface of the substrate. The antenna is accessible by coupling it to a via and, through the via, to a substrate signal bond pad and a semiconductor die signal bond pad. In one embodiment, there is at least one via in the substrate. The at least one via provides an electrical connection between a signal bond pad of the semiconductor die and the printed circuit board. The at least one via provides an electrical connection between a substrate bond pad and the printed circuit board. The at least one via also provides an electrical connection between the signal bond pad of the semiconductor die and a land that is electrically connected to the printed circuit board.

Dependencies are inferred from the claim text.