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US 6,580,774 B1Granted
Method and apparatus to perform cell synchronization in an asynchronous transfer mode network
AssigneeOccam Networks
InventorsJohn Neil Jensen, Harun Muliadi, Vardan Antonyan
Life of this patent
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Abstract
A method and apparatus for synchronizing ATM cells is disclosed. A synchronization unit receives a data clock signal and a plurality of control signals. Based on those signals, a sync pulse is generated. If synchronization is not achieved within a predetermined time period, the sync pulse is shifted one bit location. Through iterative shifting of the sync pulse, synchronization is ultimately achieved.
Claims13
An apparatus comprising:
- a synchronization unit to receive a clock for an incoming bit stream, the synchronization unit to generate a synchronization pulse to identify boundaries for the incoming bit stream;
- and
- a register coupled to the synchronization unit programmable to hold a value, the value dictating a location of the synchronization pulse in an eight bit series of the incoming bit stream, the register indicating a boundry location once synchronization is achieved.
A method comprising:
- generating a first synchronization pulse at a bit location, defined by a stored value, and a plurality of additional bit locations eight bits distant from each predecessor sync pulse;
- determining if synchronization has been achieved;
- and
- if synchronization is not achieved, iteratively shifting the bit location of the sync pulse until synchronization is achieved.
1 more element
A system comprising:
- a framer coupled to a remote endpoint;
- a cell delineation unit coupled to the framer;
- and
- a synchronization unit coupled between the framer and the cell delineation unit to iteratively generate a sync pulse responsive to a data clock from the framer by shifting a bit location of the sync pulse within a cell until synchronization is achieved.
1 more element
An apparatus comprising:
- a synchronization unit including a first counter and a plurality of XOR gates coupled to the first counter and a second counter coupled to an AND gate, the synchronization unit to receive a clock for an incoming bit stream and to generate a synchronization pulse;
- and
- a register coupled to the synchronization unit programmable to hold a value, the value dictating a location of the synchronization pulse in an eight bit series.
An apparatus comprising:
- a synchronization unit including a first counter and a plurality of XOR gates coupled to the first counter, the synchronization unit to receive a clock for an incoming bit stream and to generate a synchronization pulse;
- and
- a register coupled to the synchronization unit programmable to hold a value, the value dictating a location of the synchronization pulse in an eight bit series, wherein the XOR gates receive as inputs the three bits from the first counter and three control signals from the register.
A method comprising:
- generating a first synchronization pulse at a first bit location, defined by a supplied value, and a plurality of additional bit locations eight bits distant from each predecessor sync pulse;
- determining if synchronization has been achieved;
- and
- generating a second synchronization pulse at a second bit location if synchronization is not achieved;
- and
- iteratively shifting the bit location of the sync pulse when synchronization is not achieved within a predetermined time period.
3 more elements
A method comprising:
- generating a first synchronization pulse at a first bit location, defined by a supplied value, and a plurality of additional bit locations eight bits distant from each predecessor sync pulse;
- determining if synchronization has been achieved;
- generating a second synchronization pulse at a second bit location if synchronization is not achieved;
- wherein generating a first sync pulse comprises writing a value to register, and employing the value to specify the first bit location;
- and
- wherein generating a second sync pulse comprises writing a next value to the register and employing the next value to specify the second bit location.
3 more elements
Dependencies are inferred from the claim text.