Switched-capacitor, common-mode feedback circuit for a differential amplifier without tail current

A common-mode voltage adjusting circuit configured for cooperative arrangement with (i) a common-mode feedback module including switchable capacitors, and (ii) a differential amplifier, the amplifier having at least inverting and non-inverting input stages including respective first and second active devices, gates of the first and second active devices respectively forming inverting and non-inverting input ports and sources thereof coupled to a common amplifier node, the common-mode voltage adjusting circuit comprising:

• third and fourth active devices having gates thereof coupled together to form an adjusting signal input node and sources thereof coupled to the common amplifier node;
• wherein drains of the first and third active devices are connected together and drains of the second and fourth active devices are connected together;
• wherein during a first timing phase of operation the common-mode feedback module is configured to (i) receive output signals produced by the amplifier, (ii) receive a number of reference signals produced by reference voltage sources, (iii) compare the output signals with the number of reference signals, and (iv) produce an adjusting signal based upon the comparison;
• and
• wherein each of the third and fourth active devices is configured to (i) receive the adjusting signal via the adjusting signal input node, (ii) provide a gain to the adjusting signal in accordance with a first predetermined gain factor, and (iii) facilitate an adjustment to one or more of the number of the output signals based upon the gain during a second timing phase of operation.

An amplifier comprising:

• an input stage including two or more input transistors, gates thereof forming respective input ports, drains thereof being respectively connected, at least indirectly, to amplifier output ports, and sources thereof being connected to a common node;
• wherein the input transistors are configured to (i) receive respective input signals via the input ports, (ii) multiply the received input signals in accordance with a first predetermined gain factor, and (iii) facilitate production of respective output signals based upon the multiplied input signals;
• and
• a feedback device including two or more feedback transistors, gates of the feedback transistors being connected together to form a feedback input node, sources thereof being connected to the common node, and drains thereof being connected to the drains of the input transistors;
• wherein the feedback transistors are configured to (i) receive respective adjusting signals via the feedback input node, (ii) multiply the respective adjusting signal in accordance with a second predetermined gain factor, and (iii) adjust the respective output signals based upon the multiplied adjusting signal.

A differential amplifier comprising:

• first, second, and third pairs of transistors, sources of the first pair being connected to a first common node, drains of the first pair being connected to sources of the second pair, and drains of the second and third pairs being connected together;
• an inverting input transistor having (i) its drain connected to a source of one transistor of the third pair, (ii) its source connected to a second common node, and (iii) its gate forming an inverting input port;
• wherein the drain of the one transistor of the third pair forms a non-inverting output port;
• a non-inverting input transistor having (i) its drain connected to a source of the other transistor of the third pair, (ii) its source connected to the second common node, and (iii) its gate forming a non-inverting input port;
• wherein the drain of the other transistor of the third pair forms an inverting output port;
• a pair of feedback transistors having gates thereof connected together to form an adjusting signal input node, drains thereof respectively connected to the drains of the inverting and non-inverting input transistors, and sources thereof connected to the second common node;
• a reference voltage source configured to provide a reference voltage signal, the reference voltage source having a negative end connected to the second common node and a positive end connected to the first common node;
• a common-mode voltage source configured to produce a desirable common-mode voltage signal and having a first end connected to the second common node;
• and
• a common-mode voltage feedback module including two pairs of capacitors, the two pairs of capacitors being switchable between two or more timing phases of operation, the common-mode voltage feedback module being configured to (i) receive output signals produced by the amplifier, (ii) receive the reference voltage signal and the desirable common-mode voltage signal, (iii) compare the output signals with the reference voltage signal and the desirable common-mode voltage during a first of the two or more timing phases, and (iv) produce an adjusting signal based upon the comparison during a second of the two or more timing phases, the adjusting signal being applied to the adjusting signal input node to adjust the output signals.

A method for adjusting output common-mode voltages in an amplifier, the amplifier including at least a common-mode feedback module having input ports coupled to amplifier output ports and having an output port coupled to gates of a first pair of transistors, the common-mode feedback module being configured to switch between two or more timing phases of operation, gates of the first pair of transistors being connected together to form an adjusting signal input node, drains of the first pair of transistors being connected to drains of a second pair of transistors, and gates of the second pair of transistors forming amplifier input ports, the method comprising:

• receiving a number of reference voltage signals and output signals as inputs in the common-mode feedback module;
• comparing the reference voltage signals with the output signals and producing an adjusting signal thereby, the comparing occurring during a first of the two or more timing phases;
• receiving the adjusting signal in the first pair of transistors via the adjusting signal input node;
• applying a gain to the adjusting signal in the first pair of transistors, the gain being based upon a first predetermined gain factor;
• and
• adjusting the output signals in accordance with the applying during a second of the two or more timing phases.