Chip size semiconductor packages with stacked dies
AssigneeAmkor Technology, Inc.
InventorsThomas P. Glenn, Steven Webster, Vincent DiCaprio
Life of this patent
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Abstract
Chip-size semiconductor packages (“CSPs”) containing multiple stacked dies are disclosed. The dies are mounted on one another in a stack such that corresponding ones of the vias in the respective dies are coaxially aligned. An electrically conductive wire or pin is in each set of aligned vias and soldered to corresponding ones of the terminal pads. The pins include portions protruding from the stack of dies that serve as input-output terminals of the package. Heat spreaders can be interleaved between the stacked dies to enhance heat dissipation from the package.
Claims28
A chip size semiconductor package (“CSP”) with stacked dies, the CSP comprising:
- two or more semiconductor dies mounted on top of one another in a stack, each die having opposite first and second surfaces, an electronic IC device in the first surface thereof, a plurality of input-output terminal pads on the first surface thereof and in electrical connection with the electronic device therein, and a plurality of vias, with each said via extending through the die and a respective one of the terminal pads thereon, each said via having walls with a dielectric coating thereon and being coaxially aligned with a corresponding said via in the other dies;
- and,
- a plurality of electrically conductive pins each inserted through the coaxially aligned vias of the dies of the stack and electrically connected to corresponding ones of the terminal pads on each said die in the stack, each said pin having a portion protruding below a lower surface of a lowermost said die in the stack or an upper surface of an uppermost said die in the stack and comprising an input-output terminal of the CSP.
A semiconductor package comprising:
- first and second semiconductor dies stacked one on the other, each die having opposite active and inactive surfaces, a plurality of terminal pads on the active surface thereof, and a plurality of vias extending through each die between the active and inactive surfaces thereof,
- wherein each said via extends through one of said terminal pads and has an inner wall with a dielectric coating thereon, and each said via is coaxially aligned with a corresponding one of the vias of the other of the first and second semiconductor dies;
- and
- a plurality of electrically conductive pins, wherein each said pin extends through the coaxially aligned vias of the first and second semiconductor dies and is electrically coupled to the terminal pads of the first and second dies through which the via extends.
A semiconductor assembly comprising:
- first and second semiconductor dies stacked one on the other, each die having opposite active and inactive surfaces, and a plurality of terminal pads on the active surface, thereof;
- and
- a plurality of electrically conductive pins, wherein each said pin extends through the first and second semiconductor dies between the active and inactive surfaces thereof and through corresponding ones of the terminal pads of the first and second semiconductor dies, with each pin being electrically coupled to the terminal pads through which the pin extends, thereby electrically interconnecting the first and second semiconductor dies.
Dependencies are inferred from the claim text.