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US 6,573,777 B2Granted
Variable-delay element with an inverter and a digitally adjustable resistor
AssigneeIntel Corporation
InventorsMartin Saint-Laurent, Haytham Samarchi
Life of this patent
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Abstract
A clock distribution network is provided which includes variable-delay element. The variable-delay element consists of an inverter and a digitally adjustable resistor. The digitally adjustable resistor includes a plurality of transistors provided in plurality of rows and a plurality of columns. The variable-delay element functions logically equivalent to the inverter in which the delay is varied in accordance with the variance in resistance of the digitally adjustable resistor.
Claims10
A method of selecting a control bit combination, comprising:
- determining a minimum value and a maximum value for a range of resistance values for a plurality of legal control bit combinations;
- approximating a minimum resistance value and a maximum resistance value of a control bit combination from the plurality of legal control bit combinations for a plurality of fabrication variations;
- selecting a desired resistance value within the range between the approximated minimum resistance value and the approximated maximum resistance value;
- selecting the control bit combination based on the approximated minimum resistance value, the approximated maximum resistance value and the desired resistance value;
- and
- determining a worst-case resistance deviation from the desired resistance value.
3 more elements
An apparatus comprising:
- a variable delay element;
- and
- a processing element, coupled to the variable delay element, to
- determine a minimum value and a maximum value for a range of resistance values for a plurality of legal control bit combinations provided to the variable delay element,
- approximate a minimum resistance value and a maximum resistance value of a control bit combination from the plurality of legal control bit combinations for a plurality of fabrication variations in the variable delay element,
- select a desired resistance value within the range between the approximated minimum resistance value and the approximated maximum resistance value,
- select the control bit combination based on the approximated minimum resistance value, the approximated maximum resistance value and the desired resistance value, and
- determine a worst-case resistance deviation from the desired resistance value.
5 more elements
Dependencies are inferred from the claim text.