Silicon carbide semiconductor device

A semiconductor device comprising:

• a semiconductor substrate made of silicon carbide of a first conductivity type,
• a silicon carbide epitaxial layer of the first conductivity type which is formed on the main side of the semiconductor substrate,
• a first semiconductor region formed on said silicon carbide substrate and made of silicon carbide of a second conductivity type,
• a second semiconductor region formed on said first semiconductor region and made of silicon carbide of the first conductivity type,
• a third semiconductor region formed on said first semiconductor region, connecting said silicon carbide epitaxy layer and said second semiconductor region, made of silicon carbide of the first conductivity type said third semiconductor region comprising a fist section (5a) on said first semiconductor region and second section (5b) other than the first section on said epitaxial layer, said first section (5a) having a lower concentration than said semiconductor substrate (1), said second section (5b) being of lower resistance than said first section (5a), and
• a gate electrode formed on said third semiconductor region via an insulating layer, wherein the thickness of said third semiconductor layer is a thickness (order of sub microns) such that total depletion occurs when no voltage is being applied to said gate electrode.

A semiconductor device comprising:

• a semiconductor substrate made of silicon carbide of a first conductivity type,
• a silicon carbide epitaxial layer of the first conductivity type which is formed on the main side of the semiconductor substrate,
• a first semiconductor region formed on said silicon carbide substrate and made of silicon carbide of a second conductivity type,
• a second semiconductor region formed on said first semiconductor region and made of silicon carbide of the first conductivity type,
• a third semiconductor region formed on said first semiconductor region, connecting said silicon carbide epitaxy layer and said second semiconductor region, made of silicon carbide of the first conductivity type, the third semiconductor region comprises a first section (5a) on said first semiconductor region and a second section (5b) other than the first section on said epitaxial layer, said first section (5a) having a lower concentration than said semiconductor substrate (1), said second section (5b) being of lower resistance than said first section (5a), and
• a gate electrode formed on said third semiconductor region via an insulating layer, wherein the impurity concentration of the section of the surface channel layer situated on the surface section of the epitaxial layer is higher than that of the remaining section of the surface channel epilayer and silicon carbide epitaxial layer, thus lowering the ON resistance of the MOSFET.

A semiconductor device comprising:

• a semiconductor substrate of a first conductivity type comprising single crystal silicon carbide,
• a silicon carbide epitaxial layer of the first conductivity type which is formed on the main side of the semiconductor substrate,
• a first semiconductor region formed on said silicon carbide epitaxial layer and comprising silicon carbide of a second conductivity type,
• a second semiconductor region formed on said first semiconductor region, comprising silicon carbide of the first conductivity type and separated from the silicon carbide epitaxy layer of the first conductivity type by said first semiconductor,
• a third semiconductor region formed on said semiconductor region, connected to said silicon region, comprising silicon carbide of the first conductivity type, and of higher resistance than said semiconductor substrate,
• the third semiconductor region comprising a first section (5a) on said first semiconductor region and second section (5b) other than the first section on said epitaxial layer, said first section (5a) being of higher resistance than said semiconductor substrate, said second section (5b) being of lower resistance than said first section (5a), and
• a gate electrode formed on said third semiconductor region with an insulating layer therebetween, wherein said third semiconductor layer is depleted when no voltage is being applied to said gate electrode so that said semiconductor device has a normally-OFF characteristic, and wherein said third semiconductor region has a impurity concentration of about 1×1015 cm−3, said third semiconductor region has a thickness of greater than zero and thinner than 0.7 μm;
• and said gate electrode comprises a doped polysilicon.

A semiconductor device comprising:

• a semiconductor substrate of a first conductivity type comprising singe crystal silicon carbide
• a silicon carbide epitaxial layer of the first conductivity type which is formed on the main side of the semiconductor substrate,
• a first semiconductor region formed on said silicon carbide epitaxial layer and comprising silicon carbide of a second conductivity type,
• a second semiconductor region formed on said first semiconductor region, comprising silicon carbide of the first conductivity type and separated from the silicon carbide epitaxy layer of the first conductivity type by said first semiconductor,
• a third semiconductor region formed on said semiconductor region, connected to said silicon region, comprising silicon carbide of the first conductivity type, and of higher resistance than said semiconductor substrate,
• the third semiconductor region comprising a first section (5a) on said first semiconductor region and a second section (5b) other than the first section on said epitaxial layer, said first section (5a) being of higher resistance than said semiconductor substrate, said second section (5b) being of lower resistance than said first section (5a), and
• a gate electrode formed on said third semiconductor region with an insulating layer therebetween, wherein said third semiconductor layer is depleted when no voltage is being applied to said gate electrode so that said semiconductor device has normally-OFF characteristic, and wherein said third semiconductor region has an impurity concentration of about 1×1016 cm−3, said third semiconductor region has a thickness of greater than zero and thinner than 0.5 μm;
• and said gate electrode comprises a doped polysilicon.

A semiconductor device comprising:

• a semiconductor substrate of a first conductivity type comprising single crystal silicon carbide
• a silicon carbide epitaxial layer of the first conductivity type which is formed on the main side of the semiconductor substrate,
• a first semiconductor region formed on said silicon carbide epitaxial layer and comprising silicon carbide of a second conductivity type,
• a second semiconductor region formed on said first semiconductor region, comprising silicon carbide of the first conductivity type and separated from the silicon carbide epitaxy layer of the first conductivity type by said first semiconductor,
• a third semiconductor region formed on said semiconductor region, connected to said silicon region, comprising silicon carbide of the first conductivity type, and of higher resistance than said semiconductor substrate,
• the third semiconductor region comprising a first section (5a) on said first semiconductor region and a second section (5b) other than the first section on said epitaxial layer, said first section (5a) being of higher resistance than said semiconductor substrate, said second section (5b) being of lower resistance than said first section (5a), and
• a gate electrode formed on said third semiconductor region with an insulating layer therebetween, wherein said third semiconductor layer is depleted when no voltage is being applied to said gate electrode so that said semiconductor device has a normally-OFF characteristic, and wherein said third semiconductor region has an impurity concentration of about 1×1017 cm−3;
• said third semiconductor region has a thickness of greater than zero and thinner than 0.2 μm;
• and said gate electrode comprises a doped polysilicon.