Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsKatsuyuki Fujita, Takashi Ohsawa
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device has a memory cell array including memory cells; a reference current generating circuit which generates a reference current; a reference voltage generating circuit which generates a reference voltage in a reference node on the basis of the reference current generated by the reference current generating circuit; a first sense circuit which generates an output current on the basis of a cell current of the selected memory cell and which generates a data potential in a sense node on the basis of the output current and the reference current; and a second sense circuit which detects the data held in the selected memory cell by comparing the data potential in the sense node with the reference voltage in the reference node.
Claims22
A semiconductor memory device comprising:
- a memory cell array which includes memory cells for holding data;
- a reference current generating circuit which generates a reference current;
- a reference voltage generating circuit which generates a reference voltage in a reference node based on the reference current generated by the reference current generating circuit;
- a first sense circuit which generates an output current on the basis of a cell current of the selected memory cell and which generates a data potential in a sense node on the basis of the output current and the reference current;
- and
- a second sense circuit which detects data held in the selected memory cell by comparing the data potential in the sense node with the reference voltage in the reference node.
Dependencies are inferred from the claim text.