Non-volatile semiconductor memory device having a charge storing insulation film and data holding method therefor
AssigneeFujitsu Limited
InventorsSatoshi Torii, Hideyuki Kojima, Hiroshi Mawatari
Life of this patent
Estimating the term…
Abstract
In a flash memory having, for example, a single-gate type memory cell consisting of the gate electrode provided via a thin charge trap layer on a semiconductor substrate, there is provided a non-volatile semiconductor memory that is characterized in applying a short pulse to the memory cell to partly remove the electrons from the charge trap layer after writing the data to the memory cell. This ensures the write operation reliability of non-volatile semiconductor memory such as single-gate type flash memory or the like without changing the basic structure of the memory cell array.
Claims20
A non-volatile semiconductor memory device (EEPROM) including a memory cell array arranging a plurality of memory cells;
- enabling electrical programming through the transfer, of charges between a charge trap layer and a semiconductor substrate, in the form of a matrix, each of such cells is formed by sequentially laminating, on said semiconductor substrate, a first gate oxide film, said charge trap layer consisting of an insulation material which traps charges more easily than a silicon oxide film, a gate insulation film consisting of a second gate oxide film and a gate electrode, wherein after data is written to said memory cell, post-write operation is conducted so as to add pulse bring shorter than a pulse for erase operation.
A data holding method of a non-volatile semiconductor memory device for applying for a short period of time, a voltage equal to the voltage required to erase data stored in a memory cell, in order to add a pulse for post-write operation so as to be shorter than a pulse for erase operation to the non-volatile semiconductor memory device (EEPROM) including a memory cell array comprising the steps of:
- arranging a plurality of memory cells, enabling electrical programming through the transfer of charge between a charge trap layer and a semiconductor substrate in form of matrix, each of such cells is formed by sequentially laminating, on said semiconductor substrate, a first gate oxide film, said charge trap layer consisting of an insulation material which traps charges more easily than a silicon oxide film, a gate insulation film consisting of a second gate oxide film and a gate electrode.
An EEPROM, employing a memory cell having a charge trap layer capable of capturing charges easier than silicon oxide film;
- and being capable of writing data through an action of injecting charges into said charge trap layer, followed by an action of adding a pulse for post-write operation so as to be shorter than a pulse for erase operation.
Dependencies are inferred from the claim text.