Wide-band single-ended to differential converter in CMOS technology

A circuit for converting a single-ended input signal to a differential output signal, comprising:

• a voltage supply;
• a reference potential;
• a first stage, having an input INP with signal vi and a bias input IBIAS with signal ibias, first and second output nodes N1 and N2 with signals vi1 and vi2, respectively, said first stage providing a differential output signal at said nodes N1 and N2, said first stage having a first and a second MOS transistor of a first conductivity-type forming a differential amplifier, a first and a second resistive means connected between said voltage supply and the drain of said first and said second MOS transistor, respectively, the gate of said first MOS transistor coupled to said input INP via capacitive means CI1, and where a capacitive means CD connected across said gate and the source of said first MOS transistor compensates for a parasitic drain to reference potential capacitance CB of a tail current source, where said first stage further comprises:
• a current source having an input and a first and a second output, said input of said current source coupled to said bias input IBIAS for biasing said current source, said current source comprised of MOS transistors of a second conductivity-type;
• a first and a second current mirror, with a first and a second input each, said first and said second input of said current mirrors connected to said first and said second output of said current source, respectively, said first and said second current mirror comprised of MOS transistors of a said first conductivity-type;
• the drains of said first and said second MOS transistor coupled to said voltage supply via said first and said second resistive means, respectively;
• the drains of said first and said second MOS transistors labeled nodes N1 and N2, respectively;
• the sources of said first and said second MOS transistor joined in node T1 and coupled via said first current mirror to said reference potential;
• a fifth resistive means in series with said second current mirror coupled between said voltage supply and said reference potential;
• the gate of said first and said second MOS transistor coupled via a sixth and a seventh resistive means, respectively, to the junction between said fifth resistive means and said second current mirror;
• and
• the gate of said second MOS transistor coupled via capacitive means CI2 to said reference potential;
• a second stage connected to said nodes N1 and N2, said second stage having outputs OUTA and OUTB, said second stage having a third and a fourth MOS transistor of said first conductivity-type forming a differential amplifier, a first capacitive means CF1 connected between the drain of said third MOS transistor and the gate of said fourth MOS transistor, a second capacitive means CF2 connected between the drain of said fourth MOS transistor and the gate of said third MOS transistor, said first and said second capacitive means CF1 and CF2 each having a capacitance 5 to 10 times larger than the parasitic gate-to-drain capacitance of said third and said fourth MOS transistor, respectively, said first and second capacitive means CF1 and CF2 contributing toward a frequency response of signals vo1 and vo2 at said outputs OUTA and OUTB, ranging in frequency from 100 kHz to 1 GHz (1 GHz=109 Hertz), with a magnitude and phase error at said frequency of 1 GHz of no more than 0.015 dB (10 dB=1 Bell) and 0.15 degrees, respectively, when referenced to said signal vi at said input INP;
• and
• said first and said second stage connected between said voltage supply and said reference potential.

A method of converting a single-ended input signal to a differential output signal, comprising:

• providing a differential input stage, having a signal input INP and differential output signals;
• providing differential amplification in said differential input stage with a first and a second MOS transistor, where said first MOS transistor receives said signal input INP;
• compensating a parasitic tail current source transistor capacitance of said differential input stage with capacitive means CD connected across the gate and a source of said first MOS transistor thereby splitting the input signal voltage equally across the gate-source of said first and said second MOS transistor;
• connecting a differential output stage to said differential output signals of said input stage;
• providing said differential amplification of said differential output stage with a third and a fourth MOS transistor;
• coupling compensating capacitive means between the gates of one of said transistors of said differential output stage with the drains of the other transistor of said output stage;
• making the capacitance of said compensating capacitive means from 5 to 10 times larger than the parasitic capacitance from gate-source of said transistors of said differential output stage to compensate for negative feedback effects;
• making the transconductance of said transistors of said differential output stage larger by a factor ranging from 40 to 100 than the output conductance of the tail current source transistor of said differential output stage;
• and
• providing fully differential output signals at the output of said differential output stage ranging in frequency from 100 kHz to 1 GHz (1 GHz=109 Hertz), with a magnitude and phase error at said frequency of 1 GHz of no more than 0.015 dB (10 dB=1 Bell) and 0.15 degrees, respectively, when referenced to an signal at said input INP.