Programmable memory address and decode circuits with ultra thin vertical body transistors

A decoder for a memory device, comprising:

• a number of address lines;
• a number of output lines;
• wherein the address lines, and the output lines form an array;
• a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
• a number of single crystalline ultra thin vertical floating gate transistors that are disposed adjacent the number of vertical pillars, wherein each single crystalline vertical floating gate transistor includes;
• an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
• an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
• and
• an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;
• wherein a horizontal junction depth for the first and the second ultra thin single crystalline vertical source/drain regions is much less than a vertical length of the ultra thin single crystalline vertical body region;
• and
• a floating gate opposing the vertical body region and separated therefrom by a gate oxide;
• a plurality of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array;
• and
• wherein each of the number of address lines is disposed between rows of the pillars and opposes the floating gates of the single crystalline vertical floating gate transistors for serving as a control gate.

A programmable decode circuit for a semiconductor memory, comprising:

• a number of address lines;
• a number of output lines;
• wherein the address lines, and the output lines form an array;
• a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
• a pair of single crystalline ultra thin vertical floating gate transistors formed along opposing sides of each pillar, wherein each single crystalline vertical floating gate transistor includes;
• an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
• an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
• and
• an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;
• wherein a surface space charge region for the single crystalline vertical transistor scales down as other dimensions of the transistor scale down;
• and
• a floating gate opposing the vertical body region and separated therefrom by a gate oxide, and wherein the floating gate is formed in a trench between rows of the number of pillars and is shared between the ultra thin single crystalline vertical floating gate transistors that are adjacent the trench in column adjacent pillars;
• a plurality of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array;
• and
• wherein each of the number of address lines is disposed between rows of the pillars and opposes the floating gates of the single crystalline vertical floating gate transistors for serving as a control gate.

A decode circuit for a semiconductor memory, comprising:

• a number of address lines;
• a number of output lines;
• wherein the address lines, and the output lines form an array;
• a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
• a pair of single crystalline ultra thin vertical floating gate transistors formed opposing sides of each pillar, wherein each single crystalline vertical floating gate transistor includes;
• an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
• an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
• an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;
• and
• a floating gate opposing the vertical body region in a trench and separated therefrom by a tunnel oxide;
• and
• wherein each of the number of address lines is disposed between rows of the pillars and is shared as a control gate for addressing floating gates on opposing sides of the trench in column adjacent pillars.

A memory address decoder, comprising:

• a number of address lines;
• a number of output lines;
• wherein the address lines, and the output lines form an array;
• a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
• a pair of single crystalline ultra thin vertical floating gate transistors along opposing sides of each pillar, wherein each single crystalline vertical floating gate transistor includes;
• an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
• an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
• and
• an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;
• a floating gate opposing the vertical body region and separated therefrom by a gate oxide;
• and
• wherein each of the number of address lines is disposed in a trench between rows of the pillars and is shared as a control gate for addressing floating gates on opposing sides of the trench in column adjacent pillars.

An address decode circuit, comprising:

• a number of address lines;
• a number of data lines that are selectively coupled to the address lines;
• wherein the address lines and the data lines form an array;
• and
• a number of single crystalline ultra thin vertical floating gate transistors that are selectively disposed at intersections of data lines and address lines, wherein each single crystalline vertical floating gate transistor includes;
• an ultra thin single crystalline vertical first source/drain region;
• an ultra thin single crystalline vertical second source/drain region;
• an ultra thin single crystalline vertical body region which couples the first and the second source/drain regions;
• and
• a floating gate opposing the vertical body region and separated therefrom by a gate oxide;
• wherein each of the number of data lines is coupled to the second source/drain region in column adjacent pillars;
• and
• wherein the number of address lines integrally form control lines opposing the floating gates of the single crystalline ultra thin vertical floating gate transistors such that the single crystalline ultra thin vertical floating gate transistors implement a logic function that selects a data line responsive to an address provided to the address lines and a charge stored on the floating gates.

A memory device, comprising:

• an array of wordlines and complementary bit line pairs;
• a number of memory cells that are each addressably coupled at intersections of a word line with a bit line of a complementary bit line pair;
• a row decoder that is coupled to the wordlines so as to implement a logic function that selects one of the wordlines responsive to an address provided to the row decoder on a number of first address lines;
• a number of sense amplifiers, each coupled to a complementary pair of bit lines;
• a column decoder that is coupled to the sense amplifiers so as to implement a logic function that selects one of the complementary pairs of bit lines responsive to an address provided to the column decoder on a number of second address lines;
• and
• wherein the row decoder comprises an array of single crystalline ultra thin vertical floating gate transistors that are selectively coupled to implement a logic function that selects a wordline based on addresses supplied on the number of first address lines, wherein each single crystalline vertical floating gate transistor includes;
• an ultra thin single crystalline vertical first source/drain region;
• an ultra thin single crystalline vertical second source/drain region;
• an ultra thin single crystalline vertical body region which couples the first and the second source/drain regions
• a floating gate opposing the vertical body region and separated therefrom by a gate oxide.

An electronic system, comprising:

• a processor;
• and
• a memory device coupled to processor, wherein the memory device includes a programmable decoder comprising:
• a number of address lines;
• a number of output lines;
• wherein the address lines, and the output lines form an array;
• a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
• a pair of single crystalline ultra thin vertical floating gate transistors formed along opposing sides of each pillar, wherein each single crystalline vertical floating gate transistor includes;
• an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
• an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
• and
• an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;
• wherein a surface space charge region for the single crystalline vertical transistor scales down as other dimensions of the transistor scale down;
• and
• a floating gate opposing the vertical body region and separated therefrom by a gate oxide, and wherein the floating gate is formed in a trench between rows of the number of pillars and is shared between the ultra thin single crystalline vertical floating gate transistors that are adjacent the trench in column adjacent pillars;
• a plurality of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first contact layer of pillars in the array;
• and
• wherein each of the number of address lines is disposed between rows of the pillars and opposes the floating gates of the single crystalline vertical floating gate transistors for serving as a control gate.

A electronic system, comprising:

• a processor;
• and
• a memory device coupled to processor, wherein the memory device includes a programmable memory address decoder comprising:
• a number of address lines;
• a number of output lines;
• wherein the address lines, and the output lines form an array;
• a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
• a pair of single crystalline ultra thin vertical floating gate transistors formed on opposing sides of each pillar, wherein each single crystalline vertical floating gate transistor includes;
• an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
• an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
• an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;
• and
• a floating gate opposing the vertical body region in a trench and separated therefrom by a tunnel oxide;
• and
• wherein each of the number of address lines is disposed between rows of the pillars and is shared as a control gate for addressing floating gates on opposing sides of the trench in column adjacent pillars.

A electronic system, comprising:

• a processor;
• and
• a memory device coupled to the processor, wherein the memory device includes a memory address decoder comprising:
• a number of address lines;
• a number of output lines;
• wherein the address lines, and the output lines form an array;
• a number of vertical pillars extending outwardly from a semiconductor substrate at intersections of output lines and address lines, wherein each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer;
• a pair of single crystalline ultra thin vertical floating gate transistors along opposing sides of each pillar, wherein each single crystalline vertical floating gate transistor includes;
• an ultra thin single crystalline vertical first source/drain region coupled to the first contact layer;
• an ultra thin single crystalline vertical second source/drain region coupled to the second contact layer;
• and
• an ultra thin single crystalline vertical body region which opposes the oxide layer and couples the first and the second source/drain regions;
• a floating gate opposing the vertical body region and separated therefrom by a gate oxide;
• and
• wherein each of the number of address lines is disposed in a trench between rows of the pillars and is shared as a control gate for addressing floating gates on opposing sides of the trench in column adjacent pillars.