Back to results
US 6,563,759 B2Granted
Semiconductor memory device
AssigneeHitachi, Ltd.
InventorsHideharu Yahata, Masashi Horiguchi, Hiroki Fujisawa, Tsugio Takahashi, Masayuki Nakamura
Life of this patent
Estimating the term…
Abstract
In a clock synchronous memory like a double data rate synchronous DRAM, a register is provided which is capable of setting a value (advanced latency) for specifying an input or entry cycle for a read or write command. Further, a timing adjustment register (124, 125) for delaying a signal by a predetermined cycle time according to the advanced latency set to the register is provided on a signal path in a column address system, which is formed between a column address latch circuit (110) and a column decoder (116).
Claims25
A semiconductor memory device comprising:
- a memory-cell array having a plurality of word lines and a plurality of bit lines to which memory cells are connected;
- a row address latch circuit which latches a row address;
- a row decoder which decodes the row address to thereby select a word line lying within said memory cell array;
- a column address latch circuit which latches a column address;
- a column decoder which decodes the column address to thereby select at least one bit line lying within said memory cell array;
- an output buffer which outputs data read from said memory cell array;
- an input buffer which takes in an input data;
- a first register capable of setting values for specifying a timing provided to take the input data in said input buffer and a timing provided to output the data from said output buffer;
- a second register capable of setting a value for specifying a timing provided to input a data read command or a data write command;
- and
- a timing adjustment circuit provided on a column address signal path between said column address latch circuit and said column decoder and for delaying a signal by a predetermined time according to the value set to said second register,
- wherein said input buffer and said output buffer are configured so as to determine operating timings according to the values set to said first register.
9 more elements
A semiconductor memory device comprising:
- a circuit which adjusts a signal transmission time for a column address signal path so as to be operable in accordance with both cases in which the number of clock cycles from the input of an active command to the input of a read command is one clock cycle and more than one clock cycle.
A semiconductor memory device comprising:
- a circuit which adjusts a signal transmission time for a column address signal path so as to be operable in accordance with both cases in which the number of clock cycles from the input of an active command to the input of a write command is one clock cycle and more than one clock cycle.
A method of operating a semiconductor memory device synchronized with a clock signal and activated based on commands, comprising the steps:
- a step for inputting a first command with a first timing of the clock signal;
- a step for inputting a first address with the first timing;
- a step for inputting a second command with a second timing subsequent to a first clock cycle of the clock signal with respect to the first timing;
- a step for inputting a second address with the second timing;
- a first adjusting step for adjusting the time necessary to transmit the second address or a signal formed based on the second address;
- a step for inputting the first command with a third timing of the clock signal;
- a step for inputting a third address with the third timing;
- a step for inputting the second command with a fourth timing subsequent to a second clock cycle of the clock signal with respect to the third timing;
- a step for inputting a fourth address with the fourth timing;
- and
- a second adjusting step for adjusting the time necessary to transmit the fourth address or a signal formed based on the fourth address;
- wherein said first clock cycle and said second clock cycle are different from each other, and
- the adjustment time in said first adjusting step and the adjustment time in said second adjusting step are different from each other.
10 more elements
A method of operating a semiconductor memory device synchronized with a clock signal and activated based on commands, comprising the steps:
- a step for inputting an active command with a first timing of the clock signal;
- a step for inputting a first row address with the first timing;
- a step for inputting a read command with a second timing subsequent to a first clock cycle of the clock signal with respect to the first timing;
- a step for inputting a first column address with the second timing;
- a first adjusting step for adjusting the time necessary to transmit the first column address or a signal formed based on the first column address;
- a step for outputting data stored in a memory cell, corresponding to the first row address and the first column address to the outside of said semiconductor memory device;
- a step for inputting the active command with a third timing of the clock signal;
- a step for inputting a second row address with the third timing;
- a step for inputting the read command with a fourth timing subsequent to a second clock cycle of the clock signal with respect to the third timing;
- a step for inputting a second column address with the fourth timing;
- a second adjusting step for adjusting the time necessary to transmit the second column address or a signal formed based on the second column address;
- and
- a step for outputting data stored in a memory cell, corresponding to the second row address and the second column address to the outside of said semiconductor memory device,
- wherein said first clock cycle and said second clock cycle are different from each other, and
- the adjustment time in said first adjusting step and the adjustment time in said second adjusting step are different from each other.
12 more elements
A method of operating a semiconductor memory device synchronized with a clock signal and operated based on commands, comprising the steps:
- a step for inputting an active command with a first timing of the clock signal;
- a step for inputting a first row address with the first timing;
- a step for inputting a write command with a second timing subsequent to a first clock cycle of the clock signal with respect to the first timing;
- a step for inputting a first column address with the second timing;
- a first adjusting step for adjusting the time necessary to transmit the first column address or a signal formed based on the first column address;
- a step for inputting the active command with a third timing of the clock signal;
- a step for inputting a second row address with the third timing;
- a step for inputting the write command with a fourth timing subsequent to a second clock cycle of the clock signal with respect to the third timing;
- a step for inputting a second column address with the fourth timing;
- and
- a second adjusting step for adjusting the time necessary to transmit the second column address or a signal formed based on the second column address,
- wherein said first clock cycle and said second clock cycle are different from each other, and
- the adjustment time in said first adjusting step and the adjustment time in said second adjusting step are different from each other.
10 more elements
Dependencies are inferred from the claim text.