Motor control apparatus
AssigneeCanon Kabushiki Kaisha
InventorTetsuya Morita
Life of this patent
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Abstract
With a memory access control portion without being intermediated by control of a CPU controlling an entire drive control of a motor, velocity data for setting velocity of a motor step by step are read out from a velocity table memory, and data value read out from the velocity table are converted by a time conversion circuit to time data, and based hereon a phase switching signal to operate the motor is generated in a phase signal generating portion. In addition, outputting of next data is requested to a memory access control portion in every time data output of a time conversion apparatus and occurrence of access to a next memory table is urged.
Claims14
A motor control apparatus to drive-control a motor in a combination of a plurality of phase signals, comprising:
- a velocity table memory for storing velocity data for setting a velocity of the motor step by step;
- a CPU for controlling a drive control of the motor, said CPU outputting a start signal to start reading out velocity data from said velocity table memory;
- a memory access control portion for inputting the start signal output by said CPU and for sequentially reading out velocity data stored in a plurality of addresses from said velocity table memory without depending on any instruction from said CPU, after said memory access control portion inputs the start signal output by said CPU;
- a time conversion portion for converting velocity data read out from said velocity table memory by control of said memory access control portion to time data;
- and
- a phase signal generating portion for generating phase switching signals to operate the motor based on an output of said time conversion portion.
A motor control apparatus to drive-control a motor in a combination of a plurality of phase signals, comprising:
- a velocity table memory for storing velocity data for setting a velocity of the motor step by step;
- a CPU for controlling a drive control of the motor, said CPU outputting a start signal to start reading out velocity data from said velocity table memory;
- a memory access control portion for inputting the start signal output by said CPU and for sequentially reading out velocity data stored in a plurality of addresses from said velocity table memory without depending on any instruction from said CPU, after said memory access control portion inputs the start signal output by said CPU;
- a time conversion portion for converting velocity data read out from said velocity table memory by control of said memory access control portion to time data;
- and
- a phase signal generating portion for generating phase switching signals to operate the motor based on an output of said time conversion portion;
- and
- a control portion for controlling said time conversion portion so that velocity data that corresponds to the time data is read out from said velocity table memory until an output of said time conversion portion reaches a predetermined time.
A motor control apparatus to drive-control a motor in a combination of a plurality of phase signals, comprising:
- a velocity table memory for storing velocity data for setting a velocity of the motor step by step;
- a CPU for controlling a drive control of the motor, said CPU outputting a start signal to start reading out velocity data from said velocity table memory;
- a memory access control portion for inputting the start signal output by said CPU and for sequentially reading out velocity data stored in a plurality of addresses from said velocity table memory without depending on any instruction from said CPU, after said memory access control portion inputs the start signal output by said CPU;
- a time conversion portion for converting velocity data read out from said velocity table memory by control of said memory access control portion to time data;
- and
- a phase signal generating portion for generating phase switching signals to operate the motor based on an output of said time conversion portion;
- and
- a register for setting a skip amount to a read-out address when said memory access control portion sequentially reads out velocity data of said velocity table memory.
Dependencies are inferred from the claim text.