High speed successive approximation return path and data conversion methods and circuits using the same

A charge redistribution analog to digital converter comprising:

• comparator circuitry for comparing voltages presented at first and second comparator inputs and latching to a selected one of first and second output voltages in response;
• an array of bit-weighted capacitors coupled to a selected one of the first and second comparator inputs;
• a plurality of switches associated with a selected capacitor of said array capacitors for selectively coupling said capacitor with an input during a sampling phase and a selected one of first and second reference voltages during a conversion phase;
• a return path for controlling said plurality of switches in response to the output of the first and second voltages by the comparator circuitry, said return path including a set of latches for selectively opening ones of said plurality of switches when reset and selectively closing ones of said plurality of switches during when set, the reset and set operations non-overlapping, wherein said return path is operable during the conversion phase of a selected bit to:
• decouple a capacitor representing the selected bit from a current one of the first and second reference voltage by resetting a corresponding latch during a first part of a test period for the selected bit;
• couple the capacitor representing the selected bit to the first reference voltage during a second part of the test period for the selected bit by setting a corresponding latch;
• and
• selectively couple the capacitor representing the selected bit to a selected one of the first and second reference voltages concurrent with a test period for a subsequent bit by setting a corresponding latch.

A return path for use in a switched capacitor circuit including an array of capacitors and a plurality of switches for selectively coupling voltages to said capacitors comprising:

• a set of latches for selectively controlling said plurality of switches during time periods partitioned into non-overlapping reset and set cycles and operable to:
• decouple a selected one of the capacitors from a current voltage in the reset cycle of a first time period;
• coupling the selected capacitor to a selected reference voltage in the set cycle of the first time period;
• decouple the selected capacitor from the selected reference voltage during a reset cycle of a second time period;
• and
• selectively recoupling the selected capacitor to the selected reference voltage during the second time period in response to an output of a comparator forming a portion of said switched capacitor circuit.