Method for prototyping asynchronous circuits using synchronous devices

A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for prototyping an asynchronous circuit, the method comprising:

• receiving a design of the asynchronous circuit, the design including asynchronous cells;
• mapping an asynchronous cell of the asynchronous circuit onto a synchronous cell within a clocked synchronous device thereby creating a mapped circuit, wherein the synchronous cell simulates an operation of the asynchronous cell and wherein mapping the asynchronous cell involves:
• mapping an SR flip-flop in a control path of the asynchronous cell to a first clocked D-type master-slave flip-flop in the synchronous cell,
• mapping a pass-gate and a sticky-buffer in a data path of the asynchronous cell to a second clocked D-type master-slave flip-flop in the synchronous cell, wherein the first clocked D-type master-slave flip-flop indicates that the second clocked D-type master-slave flip-flop is one of empty and full,
• mapping a first gated clock to the first clocked D-type master-slave flip-flop, and
• mapping a second gated clock to the second clocked D-type master-slave flip-flop;
• implementing the mapped circuit on the clocked synchronous device to perform functions mapped from the asynchronous circuit;
• operating the clocked synchronous device;
• and
• using a result of operating the clocked synchronous device to verify the design of the asynchronous circuit.

A method for prototyping an asynchronous circuit, comprising:

• receiving a design of the asynchronous circuit, the design including asynchronous cells;
• mapping the asynchronous circuit onto a globally clocked programmable synchronous device, wherein the globally clocked programmable synchronous device simulates an operation of the asynchronous circuit wherein the globally clocked programmable synchronous device includes a field-programmable gate-array that is mapped using a system supplied by a manufacturer of the field-programmable gate-array;
• programming the globally clocked programmable synchronous device to perform functions mapped from the asynchronous circuit;
• operating the globally clocked programmable synchronous device;
• and
• using a result of operating the globally clocked programmable synchronous device to verify the design of the asynchronous circuit.

A method for prototyping an asynchronous circuit, comprising:

• receiving a design of the asynchronous circuit, the design including asynchronous cells;
• mapping an asynchronous cell of the asynchronous circuit onto a synchronous cell within a clocked synchronous device thereby creating a mapped circuit, wherein the clocked synchronous device is one of a field-programmable gate array and a standard cell gate array, and wherein the synchronous cell simulates an operation of the asynchronous cell;
• implementing the mapped circuit on the clocked synchronous device to perform functions mapped from the asynchronous circuit;
• operating the clocked synchronous device;
• and
• using a result of operating the clocked synchronous device to verify the design of the asynchronous circuit.

A method for prototyping an asynchronous circuit, comprising:

• receiving a design of the asynchronous circuit, the design including asynchronous cells;
• mapping an asynchronous cell of the asynchronous circuit onto a synchronous cell within a clocked synchronous device thereby creating a mapped circuit, wherein the synchronous cell simulates an operation of the asynchronous cell and wherein mapping the asynchronous cell involves:
• mapping an SR flip-flop in a control path of the asynchronous cell to a first data recirculation flip-flop in the synchronous cell,
• mapping a pass-gate and a sticky-buffer in a data path of the asynchronous cell to a second data recirculation flip-flop in the synchronous cell, wherein the first data recirculation flip-flop indicates that the second data recirculation flip-flop is one of empty and full,
• mapping a first recirculation control signal to the first data recirculation flip-flop, and
• mapping a second recirculation control signal to the second data recirculation flip-flop;
• implementing the mapped circuit on the clocked synchronous device to perform functions mapped from the asynchronous circuit;
• operating the clocked synchronous device;
• and
• using a result of operating the clocked synchronous device to verify the design of the asynchronous circuit.

A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for prototyping an asynchronous circuit, the method comprising:

• receiving a design of the asynchronous circuit, the design including asynchronous cells;
• mapping an asynchronous cell of the asynchronous circuit onto a synchronous cell within a clocked synchronous device thereby creating a mapped circuit, wherein the synchronous cell simulates an operation of the asynchronous cell and wherein mapping the asynchronous cell involves:
• mapping an SR flip-flop in a control path of the asynchronous cell to a first data recirculation flip-flop in the synchronous cell,
• mapping a pass-gate and a sticky-buffer in a data path of the asynchronous cell to a second data recirculation flip-flop in the synchronous cell, wherein the first data recirculation flip-flop indicates that the second data recirculation flip-flop is one of empty and full,
• mapping a first recirculation control signal to the first data recirculation flip-flop, and
• mapping a second recirculation control signal to the second data recirculation flip-flop;
• implementing the mapped circuit on the clocked synchronous device to perform functions mapped from the asynchronous circuit;
• operating the clocked synchronous device;
• and
• using a result of operating the clocked synchronous device to verify the design of the asynchronous circuit.

A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for prototyping an asynchronous circuit, the method comprising:

• receiving a design of the asynchronous circuit, the design including asynchronous cells;
• mapping an asynchronous cell of the asynchronous circuit onto a synchronous cell within a clocked synchronous device thereby creating a mapped circuit, wherein the synchronous cell simulates an operation of the asynchronous cell and wherein mapping the asynchronous cell involves:
• mapping an SR flip-flop in a control path of the asynchronous cell to a first data recirculation flip-flop in the synchronous cell,
• mapping a pass-gate and a sticky-buffer in a data path of the asynchronous cell to a second data recirculation flip-flop in the synchronous cell, wherein the first data recirculation flip-flop indicates that the second data recirculation flip-flop is one of empty and full,
• mapping a first recirculation control signal to the first data recirculation flip-flop, and
• mapping a second recirculation control signal to the second data recirculation flip-flop;
• implementing the mapped circuit on the clocked synchronous device to perform functions mapped from the asynchronous circuit;
• operating the clocked synchronous device;
• and
• using a result of operating the clocked synchronous device to verify the design of the asynchronous circuit.

A method for prototyping an asynchronous circuit, comprising:

• receiving a design of the asynchronous circuit, the design including asynchronous cells;
• mapping the asynchronous circuit onto a globally clocked programmable synchronous device, wherein the globally clocked programmable synchronous device simulates an operation of the asynchronous circuit and wherein the globally clocked programmable synchronous device is a cell within a standard cell library that is mapped using a system supplied by a supplier of the standard cell library;
• programming the globally clocked programmable synchronous device to perform functions mapped from the asynchronous circuit;
• operating the globally clocked programmable synchronous device;
• and
• using a result of operating the globally clocked programmable synchronous device to verify the design of the asynchronous circuit.