Scheduling method for high-level synthesis and recording medium
AssigneeSharp Kabushiki Kaisha
InventorKoichi Nishida
Life of this patent
Estimating the term…
Loading patent…
AssigneeSharp Kabushiki Kaisha
InventorKoichi Nishida
Estimating the term…
The present invention relates to a scheduling method and apparatus for high-level synthesis of a circuit which is represented by an operation description. The method includes calculating a probability for each of a plurality of nodes included in a control flow graph to be assigned to a time step and calculating a sum of the probabilities for each time step. For each node having a scheduling candidate in a time step for which the sum of probabilities is maximum, an estimated value of an area of the circuit is calculated with the node having been temporarily assigned to the scheduling candidate and a combination of a node and a scheduling candidate for which the estimated value is maximum is retrieved. Finally, a list of scheduling candidates of the node in the combination is narrowed down by excluding the scheduling candidate in the combination from the list of scheduling candidates of the node in the combination.
A scheduling method for high-level synthesis of a circuit which is represented by an operation description, the method comprising the steps of:
A computer-readable recording medium having a program recorded thereon for instructing a computer to execute a scheduling method for high-level synthesis of a circuit which is represented by an operation description, the scheduling method comprising the steps of:
Dependencies are inferred from the claim text.