Method of extracting timing characteristics of transistor circuits, storage medium storing timing characteristic library, LSI designing method, and gate extraction method

A method of generating timing characteristic data of a circuit module from first circuit module data expressed by transistors, comprising the steps of:

• constructing second circuit module data expressed by gate circuits and bistable circuits from the first circuit module data;
• recognizing a first bistable circuit which is the first bistable circuit which would be reached by a signal applied to an input terminal of the circuit module, and recognizing a last bistable circuit which is the last bistable circuit which would have an effect upon a signal output from an output terminal of the circuit module;
• searching for a first path, a first clock path, a second path and second clock path;
• the first path comprising gate circuits between the input terminal and the first bistable circuit, the first clock path comprising gate circuits between a clock terminal of the circuit module and the first bistable circuit, the second path comprising gate circuits between the last bistable circuit and the output terminal and the second clock path comprising gate circuits between the clock terminal and the last bistable circuit,
• calculating an output delay of the circuit module based on a delay of the second path and a delay of the second clock path;
• and
• calculating an input timing rule of the circuit module based on setup time and hold time of the bistable circuit, a delay of the first path and a delay of the first clock path.