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US 6,557,143 B1Granted
Computer aided design system and computer-readable medium storing a program for designing clock gated logic circuits and gated clock circuit
AssigneeKabushiki Kaisha Toshiba
InventorsTakeshi Kitahara, Takashi Ishikawa, Kimiyoshi Usami
Life of this patent
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Abstract
A computer aided design system and a method for clock gated logic circuits, a computer-readable medium for storing the same and a gated clock circuit are provided in which the clock skew is suppressed within a tolerable level without increasing the electric power consumption.
Claims3
A gated clock system comprising:
- a plurality of storage elements which are grouped into a plurality of partial trees;
- a plurality of gating circuits provided respectively for said partial trees in order to control a clock signal supplied to each of said partial trees respectively in accordance with a logic sum of enable logics of said storage elements belonging to said partial trees,
- wherein at least one of said partial trees has at least one of said storage elements having a feedback loop and at least one of said storage elements having no feedback loop,
- wherein said storage elements are grouped into the plurality of partial trees so that a disparity in a number of said storage elements belonging to said partial trees is not greater than 5%.
1 more element
Dependencies are inferred from the claim text.