US 6,557,138 B1Granted

Method for correction of errors in a binary word stored in multi-level memory cells, with minimum number of correction bits

AssigneeSTMicroelectronics S.r.l.

InventorAlberto Modelli

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Abstract

A method for correction of errors in a word stored in multi-bit memory cells includes associating a full error code, which includes bit error codes and a set error code, for each set of bits of the word stored in a single memory cell. The method includes associating, with each single error, a bit error code which is not associated with other errors and which is indicative of a position of the bit in the word. The set error code is computed based on the bit error codes associated with the bits in the set. The method also checks to make sure that the full error code for the set has not already been associated with other errors. If the error code has already been used for another error, then the method changes both the set error code and at least one of the bit error codes.

Claims23

Dependent claims

Method for correction of errors in a binary word stored in multi-level memory cells, each of which contains a set of n bits, using a minimum number of correction bits, wherein for each set of bits in said binary word stored in a single memory cell, the method comprises the following steps:

a) associating, with a single error in each bit in said set of bits, a respective error code which is not associated with other errors in said binary word and is indicative of a position of the incorrect bit in the binary word;
b) for each sub-set of multiple errors in bits in said set of bits, carrying out the following steps:
b1) associating, with said sub-set of multiple errors, a respective error code which is dependent on the error codes associated with the single errors in the bits in the sub-set;
b2) checking whether the error code associated with said sub-set of multiple errors has already been associated with other errors in said binary word;
b3) if the error code associated with said sub-set of multiple errors has already been associated with other errors in said binary word, carrying out the following steps:
b31) rejecting said error code associated with said sub-set of multiple errors and at least one of the error codes associated with the single errors in the bits in the sub-set;
b32) associating, with the single error associated with the error code rejected, a new error code which is not associated with other errors in said binary word;
and
b33) repeating said steps from b1) to b3) until the error code associated with said sub-set of multiple errors is not associated with other errors in said binary word.

6 more elements

A correction system for correction of errors in a binary source word having m bits, comprising:

a group of multi-level memory cells, each of which contains a respective set of plural bits of the source word;
a decoder stage having an input that receives a check word and an output at which a correction word is produced based on the check word, the correction word having 3 m/2 correction bits including a correction bit for each bit of the source word and a correction bit for each set of plural bits of the source word;
m OR gates organized into pairs of first and second OR gates, each pair corresponding to a respective set of plural bits of the source word, the first OR gate having a first input that receives a first correction bit corresponding to a first bit of the corresponding set of plural bits of the source word, a second input that receives a second correction bit corresponding to first and second bits of the corresponding set of plural bits, and an output;
and the second OR gate having a first input that receives a third correction bit corresponding to the second bit of the corresponding set of plural bits of the source word, a second input that receives the second correction bit, and an output;
and
m exclusive-OR gates organized into pairs of first and second exclusive-OR gates corresponding respectively to the pairs of OR gates, the first exclusive-OR gate of each pair having a first input that receives the first bit of the corresponding set of plural bits of the source word, a second input coupled to the output of the first OR gate of the corresponding pair of OR gates, and an output;
and the second exclusive-OR gate of each pair having a first input that receives the second bit of the corresponding set of plural bits of the source word, a second input coupled to the output of the second OR gate of the corresponding pair of OR gates, and an output;
the outputs of the m exclusive-OR gates together output a corrected word that corresponds to the source word with individual errors in the source word being corrected.

5 more elements

Dependencies are inferred from the claim text.