Scaling logic for event based test system

An event based test system for testing an electronics device under test (DUT) by supplying a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal, comprising:

• an event memory configured by an event count memory for storing event count data of timing data which is formed with an integer multiple of a reference clock period (integral part data), and an event vernier memory for storing event vernier data of the timing data which is formed with a fraction of the reference clock period (fractional part data), wherein the timing data represents a time difference between two adjacent events;
• an address sequencer for generating address data for accessing the event memory to read out the timing data therefrom;
• a summing and scaling logic for summing the timing data of previous events and a current event from the event memory and to produce an overall time of the current event relative to a predetermined reference point, the summing and scaling logic scaling the timing data thereby changing the overall time of the current event in proportion to a scale factor, wherein the summing and scaling logic includes a delay means for providing an additional delay of one reference clock period every time when a sum of a fractional part incorporated in the summing and scaling operation exceeds the reference clock period;
• an event generator circuit for generating each event based on the overall time for formulating the test signal or strobe signals;
• and
• a host computer for controlling an overall operation of the event based test system through a test program.