Method and system for determining common failure modes for integrated circuits

A method for determining common failure modes of a quantity of integrated circuit devices under test, the method comprising:

• applying a test pattern to a series of inputs of each device under test;
• comparing a set of output data of a particular device under test to a set of expected data, said set of output data generated by the particular device under test in response to said test pattern;
• determining whether said set of output data generated by the device under test has passed the test, said set of output data passing the test if said set of output data matches said set of expected data being pass data if said set of output data does not match said set of expected data being fail data;
• storing an output signature corresponding to said set of output data if said set of output data has not passed the test;
• determining whether any stored output signatures are repeating stored signatures, wherein a specific stored output signature is a repeating stored signature if said specific stored output signature has been stored more than once;
• retesting each device having a repeated stored signature;
• and
• collecting fail data corresponding to said repeated stored signature of each device retested.

A storage medium encoded with a machine readable computer program code for determining common failure modes of an integrated circuit device under test, the storage medium including instructions for causing a computer to implement a method, the method comprising:

• applying a test pattern to a series of inputs of the device under test;
• comparing a set of output data generated by the device under test to a set of expected output data, said set of output data generated by the device under test in response to said test pattern;
• determining whether said set of output data generated by the device under test has passed the test, said set of output data passing the test if said set of output data matches said set of expected data being pass data if said set of output data does not match said set of output data being fail data;
• and
• if said set of output data has not passed the test, then:
• determining whether an output signature corresponding to said set of output data matches a previously stored output signature;
• and
• storing fail data corresponding to said output signature if said output signature matches a previously stored output signature.

A computer data signal for determining common failure modes of an integrated circuit device under test, the computer data signal comprising code configured to cause a processor to implement a method, the method comprsing:

• applying a test pattern to a series of inputs of the device under test;
• comparing a set of output data generated by the device under test to a set of expected output data, said set of output data generated by the device under test in response to said test pattern;
• determining whether said set of output data generated by the device under test has passed the test, said set of output data passing the test if said set of output data match said set of expected data being pass data if said set of output data does not match said set of output data being fail data;
• and
• if said set of output data has not passed the test, then:
• determining whether an output signature corresponding to said set of output data matches a previously stored output signature;
• and
• storing fail data corresponding to said output signature if said output signature matches a previously stored output signature.