Semiconductor test system supporting multiple virtual logic testers
AssigneeAdvantest Corporation
InventorJames Alan Turnquist
Life of this patent
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Abstract
A single semiconductor test system which behaves as multiple logic testers, each operating separately and asynchronously from the other. The semiconductor test system includes a host computer for controlling an overall operation of the test system by executing a test program, a plurality of pin-units each having means for generating a test pattern to an assigned pin of a semiconductor device under test (DUT) and evaluating a resultant response of the DUT, a pin-unit bus provided between said host computer and the plurality of pin-units for transmitting data, address, control signals and clocks, and means for configuring the pin-units corresponding to input/output pins of devices under test when a group selection address is placed on the pin-unit bus by the host computer.
Claims16
A semiconductor test system supporting multiple virtual testers for testing a plurality of devices in parallel, comprising:
- a host computer controlling an overall operation of the test system by executing a test program;
- a plurality of pin-units each having means for generating a test pattern to an assigned pin of a semiconductor device under test and evaluating a resultant response of the device under test;
- a pin-unit bus provided between said host computer and said plurality of pin-units for transmitting data, address, control signals and clocks;
- and
- means for reconfiguring said pin-units either statically or dynamically with respect to groups of test pins of the semiconductor test system where an operational timing of each of the groups of the test pins is independent from one another.
A semiconductor test system supporting multiple virtual testers for testing a plurality of devices in parallel, comprising:
- a host computer controlling an overall operation of a semiconductor test system by executing a test program;
- a plurality of pin-units each having means for generating a test pattern to an assigned pin of a semiconductor device under test and evaluating a resultant response of the device under test;
- a pin-unit bus provided between said host computer and said plurality of pin-units for transmitting data, address, control signals and clocks;
- means for configuring said pin-units statically or dynamically corresponding to test pins of the semiconductor test system when a group selection address is placed on said pin-unit bus by said host computer;
- and
- means for starting and ending a test process for each pin-unit, thereby running the pin-unit independently from other pin-units;
- wherein each pin-unit tests one of the devices under test either synchronously or asynchronously with other pint-units.
Dependencies are inferred from the claim text.