Method and apparatus for testing multi-port memories
AssigneeCadence Design Systems, Inc.
InventorsR. Dean Adams, Thomas J. Eckenrode, Steven L. Gregor, Kamran Zarrineh
Life of this patent
Estimating the term…
Abstract
A method and system for testing multiported memories, especially when one or more of the ports are not directly accessible without intervening logic. The method and system segregates the multiported memory into at least two portions which are then used for testing the one or more ports which are not directly accessible.
Claims18
A method of testing a multiported memory having first and second read and write ports, the first read and the first write port not being directly observable, and the data written by the first write port is a function of the first read port, the method comprising the steps of:
- segregating the memory into a first section;
- and
- assigning the physical address of the first section so that the second read port can read the data written from the first write port.
A method of testing a multiported memory having first and second read and write ports, the first read and the first write port not being directly observable, and the output of the first read port providing input to the first write port, the method comprising the steps of:
- segregating the memory into a first section;
- and
- assigning the physical address of the first section so that the second read port can read the data written from the first write port;
- writing data to the first section using the second write port;
- reading the written data using the second read port;
- segregating the memory into a second section;
- assigning the physical address of the first section so that the second read port cannot read the data written to this address;
- assigning the physical address of the second section so that the second read port can read the data written from the first write port;
- writing data to the second section using the second write port;
- and
- reading the data written to the second section using the first read port.
An apparatus for testing a multiported memory having first and second read and write ports, the first read and the first write port not being directly observable, and the output of the first read port providing input to the first write port, the apparatus comprising:
- means for segregating the memory into a first section;
- and
- means for assigning the physical address of the first section so that the second read port can read the data written from the first write port.
Dependencies are inferred from the claim text.