Microcomputer debug architecture and method
AssigneeSTMicroelectronics S.r.l.
InventorsDavid Alan Edwards, Anthony Willis Rich
Life of this patent
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Abstract
A computer system, comprising at least one central processing unit and a memory unit coupled to the at least one central processing unit, a set of watchpoints defined in the computer system; each watchpoint in the set of watchpoints comprising a programmable precondition register and a programmable action register, a set of latches, and selection circuitry that selects one latch in the set of latches to couple an output of an action register to an input of the selected latch.
Claims35
A computer system, comprising:
- at least one central processing unit;
- a memory unit coupled to the at least one central processing unit,
- a set of watchpoints defined in the computer system, each watchpoint in the set of watchpoints comprising a programmable precondition register and a programmable action register;
- a set of latches;
- and
- selection circuitry that selects one latch in the set of latches to couple an output of an action register to an input of the selected latch.
A computer system, comprising:
- at least one central processing unit;
- a memory unit coupled to the at least one central processing unit;
- a set of watchpoints defined in the computer system;
- and
- means for linking one watchpoint in the set of watchpoints with at least one other watchpoint in the set of watchpoints, wherein the means for linking is programmable;
- wherein the means for linking includes, associated with each watchpoint, a programmable precondition register that stores a set of precondition codes, wherein the set of precondition codes is identical for each watchpoint in the set of watch points.
A method of operating a computer system comprising at least one central processing unit and a memory unit coupled to the at least one central processing unit, the method comprising the steps of:
- defining a set of watchpoints in the computer system by defining a set of precondition registers and a set of action registers;
- defining a set of identical precondition codes to be applied to each watchpoint in the set of watchpoints;
- defining a set of identical action codes to be applied to each watchpoint in the set of watchpoints;
- storing the set of precondition codes in each precondition register in the set of precondition registers;
- storing the set of action codes in each action register in the set of action registers;
- selecting which precondition codes in the set of precondition codes are to be active for a particular watchpoint;
- selecting which action code in the set of action codes are to be active for a particular watchpoint;
- operating the computer system so as to execute a program;
- comparing the debugging data in the computer system with the active precondition codes for a particular watchpoint;
- sending a signal to the action register for the particular watchpoint when the debugging data in the computer system satisfies the active precondition codes for the particular watchpoint;
- and
- wherein the computer system responds to the active action code by generating a trigger signal and the computer system further responds to the trigger signal by setting or clearing a latch in response to a state of the trigger signal.
Dependencies are inferred from the claim text.