Built-in self test for PLL module with on-chip loop filter

A method of performing a built-in self test for a phase locked loop module, comprising the steps of:

• (A) setting a first counter value based upon a phase locked loop output clock signal;
• (B) setting a second counter value based upon a reference clock signal;
• (C) generating a match signal in response to the second counter value reaching a terminal count value;
• and
• (D) generating a pass/fail status signal based upon (i) an evaluation of an arrival time of the match signal and a most significant bit value of the first counter value and (ii) a particular test mode.

A method of performing a built-in self test for a phase locked loop module, comprising the steps of:

• (A) performing a first test sequence to verify a capability to increase a frequency of a phase locked loop output clock signal relative to a reference clock signal;
• (B) performing a second test sequence to verify a capability to decrease the frequency of the phase locked loop output clock signal relative to the reference clock signal;
• and
• (C) performing a closed loop test sequence to verify if the phase locked loop output clock signal meets a predetermined criteria for close loop phase locked loop module operation.

An on chip apparatus connectable to a phase locked loop module, the apparatus comprising:

• means for generating a first counter value in response to a clock signal generated by the phase locked loop module;
• means for generating a second counter value in response to a reference clock signal receivable by the phase locked loop module;
• means for generating a match signal in response to the second counter value reaching a terminal count value;
• and
• means for generating a status signal in response to the match signal and a most significant bit value of the first counter value.