Power-saving mode release error detection and recovery logic circuit for microcontroller devices

A microcontroller comprising:

• a clock generator for generating a microcontroller system clock signal, the microcontroller having a power-saving mode during activation of which the clock generator ceases generating the microcontroller system clock signal to reduce power consumption by said microcontroller;
• at least one data port sensing circuit for sensing a level of at least one data signal;
• a power-save release detection circuit coupled to said at least one data port sensing circuit, for detecting a transition in the level of the at least one data signal during operation in said power saving mode, and for generating a power-save mode release signal to release said clock generator from the power saving mode upon the transition in the level of the at least one data signal;
• and
• a logic gate circuit having a first input for receiving the power-save release signal, a second input for receiving a system reset signal to reset a system on which said microcontroller is mounted and an output for providing an oscillation start signal when at least one of the power-save mode release signal and the system reset signal is activated, whereby said clock generator initiates generation of the microcontroller system clock signal in response to the oscillation start signal.

A microcontroller comprising:

• a clock generator for generating a microcontroller system clock signal, the microcontroller having a power-saving mode during activation of which the clock generator ceases generation of the microcontroller system clock signal;
• a data input terminal for receiving a data signal;
• a power supply terminal for providing a power supply voltage;
• a pull-up resistor having a first end coupled to said power supply terminal, and a second end;
• a semiconductor switch having a pair of current-conducting path terminals coupled between the second end of said pull-up resistor and said data input terminal, and a control terminal;
• a pull-up-resistor enable register for storing a pull-up-resistor enable signal;
• a first inverter gate having an input coupled to receive the pull-up-resistor enable signal and an output coupled to the control terminal of said semiconductor switch;
• a level transition detection circuit for detecting a transition in the level of the data signal to generate a level transition detection signal;
• a second inverter gate having an input coupled to receive the pull-up-resistor enable signal, and an output;
• an OR logic gate having a first input coupled to receive the level transition detection signal, a second input coupled to the output of said second inverter gate, and an output;
• and
• an AND logic gate having a first input coupled to the output of said OR logic gate, a second input coupled to receive a power-save signal, which, when active, causes the microcontroller to enter power saving mode, and an output for providing a power-save release signal to release said clock generator from the power saving mode when both of the level transition detection signal and the power-save signal become active, whereby said clock generator resumes generation of the microcontroller system clock signal in response to the power-save release signal.

A microcontroller comprising:

• a clock generator for generating a microcontroller system clock signal, the microcontroller having a power-saving mode during activation of which the clock generator ceases generation of the microcontroller system clock signal;
• an output port data register for storing a data bit;
• an output port control register for storing an open-drain output mode enable signal;
• a first NOR logic gate having a first input coupled to receive the open-drain output mode enable signal, a second input coupled to receive an output disable signal, and an output;
• a NAND logic gate having a first input coupled to receive the data bit, a second input coupled to the output of said first NOR logic gate, and an output;
• a second NOR logic gate having a first input coupled to receive the open-drain output mode enable signal, a second input coupled to receive the data bit, and an output;
• a data output terminal for providing a data signal corresponding to the data bit;
• a first power supply terminal for providing an upper power supply voltage;
• a second power supply terminal for providing a lower power supply voltage;
• a first semiconductor switch having a pair of current-conducting path terminals coupled between said first power supply terminal and said data output terminal, and a control terminal coupled to the output of said NAND logic gate;
• a second semiconductor switch having a pair of current-conducting path terminals coupled between said data output terminal and said second power supply terminal, and a control terminal coupled to the output of said second NOR logic gate;
• a level transition detection circuit for detecting a transition in the level of the data signal to generate a level transition detection signal;
• an inverter gate having an input coupled to receive the open-drain output mode enable signal, and an output;
• an OR logic gate having a first input coupled to receive the data bit, a second input coupled to receive the level transition detection signal, a third input coupled to the output of said inverter gate, and an output;
• and
• an AND logic gate having a first input coupled to the output of said OR logic gate, a second input coupled to receive a power-save signal which, when active, causes the microcontroller to enter power saving mode, and an output for providing a power-save release signal to release said clock generator from the power saving mode when both of the level transition detection signal and the power-save signal become active, whereby said clock generator resumes generation of the microcontroller system clock signal in response to the power-save release signal.