Processors with data typer and aligner selectively coupling data bits of data buses to adder and multiplier functional blocks to execute instructions with flexible data types
AssigneeIntel Corporation
InventorsKumar Ganapathy, Ruban Kanapathipillai
Life of this patent
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Abstract
A signal processor with an instruction set architecture (ISA) for flexible data typing, permutation, and type matching of operands. The signal processor includes a data typer and aligner to support flexible data typing, permutation and type matching of operands of the instruction set architecture. The data typer and aligner is selectively configued to align and select one of more sets of data bits from one or more data buses as operands for functional blocks of the signal processor in response to fields of an instruction.
Claims33
A signal processor for performing digital signal processing instructions with operands having flexible data types, the signal processor comprising:
- at least one signal processing unit having,
- a first adder configured to add a pair of operands together;
- a first multiplier configured to multiply a pair of operands together;
- and
- a data typer and aligner configured to align and select a set of data bits on a first data bus as a first operand to couple into the first multiplier or the first adder, the alignment and selection of the set of data bits on the first data bus responsive to a first data type field.
A signal processor to execute digital signal processing instructions having operands with flexible data types, the signal processor comprising:
- a plurality of signal processing units having,
- a first adder configured to add a pair of operands together;
- a first multiplier configured to multiply a pair of operands together;
- and
- a data typer and aligner coupled to the first adder and the first multiplier,
- the data typer and aligner configured to align and selectively select a first set of data bits on a first data bus as a first operand for coupling into the first multiplier or the first adder responsive to a first data type field, and
- the data typer and aligner configured to align and selectively select a second set of data bits on a second data bus as a second operand for coupling into the first multiplier or the first adder responsive to a second data type field.
A signal processor to execute digital signal processing instructions having operands with flexible data types, the signal processor comprising:
- an instruction decoder to decode a digital signal processing instruction and read a first data type field, a second data type field, and a permute field;
- a plurality of signal processing units having,
- a first adder configured to add a pair of operands together;
- a first multiplier configured to multiply a pair of operands together;
- and
- a data typer and aligner coupled to the first adder and the first multiplier,
- the data typer and aligner configured to align and selectively select a first set of data bits on a first data bus as a first operand for coupling into the first multiplier or the first adder responsive to the first data type field and the permute field, and
- the data typer and aligner configured to align and selectively select a second set of data bits on a second data bus as a second operand for coupling into the first multiplier or the first adder responsive to a second data type field and the permute field.
A signal processor to execute digital signal processing instructions having operands with flexible data types, the signal processor comprising:
- a first signal processing unit having,
- a first adder configured to add a first pair of operands together;
- a first multiplier configured to multiply the first pair of operands together;
- and
- a first data typer and aligner coupled to the first adder and the first multiplier, the first data typer and aligner in response to a pair of data types to select the first pair of operands from a plurality of bits and to couple the first pair of operands to the first adder and the first multiplier.
Dependencies are inferred from the claim text.