Methods and apparatus for scalable instruction set architecture with dynamic compact instructions

A process for dynamically creating a task specific instruction comprising the steps of:

• storing m-bit instructions at addresses of a partitioned indirect very long instruction word memory (VIM);
• selecting a partition of the partitioned VIM;
• generating a VIM address of the selected partition utilizing VIM offset bits in a n-bit compacted instruction, where m>n;
• reading an rn-bit instruction from VIM at the generated VIM address;
• and
• combining bit fields from the n-bit compacted instruction and the rn-bit instruction to create the task specific instruction.

An indirect very long instruction word (iVLIW) processor comprising:

• a plurality of execution units capable of performing a plurality of distinct operations in parallel;
• a VLIW memory (VIM) for storing VLIWs, said VIM divided into VIM sections, each VIM section associated with one of said plurality of execution units, said VIM sections for storing VIM instructions in memory slots;
• an addressing mechanism using address information contained in compacted instructions to provide access to the VIM instructions in the memory slots for input to a translation mechanism;
• and
• the translation mechanism for dynamically translating compacted instructions into uncompacted instructions utilizing the VIM instructions.

An indirect very long instruction word (iVLIW) processor comprising:

• a first instruction register for receiving an n-bit compact instruction;
• a predecoder for determining from an opcode bit field of the n-bit compact instruction the functional type of translation required;
• and
• a translation processor for incorporating bits from the compact instruction to translate the n-bit compact instruction into an m-bit uncompacted instruction, where m>n.