Column address path circuit and method for memory devices having a burst access mode

A burst controller, comprising

• a first address latch receiving a first external column address, the first address latch being structured to store the first external column address and to couple the stored address to an output terminal;
• a second address latch receiving a second external column address, the second address latch being structured to store the second external column address and to couple the stored address to an output terminal;
• a third address latch receiving a third external column address, the third address latch being structured to store the third external column address and to couple the stored address to an output terminal;
• a burst counter generating a plurality of count bits corresponding to a counted column address;
• a first multiplexer having first and second input terminals, the first input terminal being coupled to the output terminal of the second address latch to receive the stored second external column address, and the second input terminal being coupled to the output terminal of the second address latch through an inverter to receive the complement of the stored second external column address, the first multiplexer further including a third input terminal coupled to the burst counter to receive one of the count bits, the first multiplexer having a control input and being operable to couple the first and second input terminals to respective first and second output terminals responsive to a first state of the control signal, and to couple the third input terminal to one of the first and second output terminals responsive to a second state of the control signal;
• a second multiplexer having first and second input terminals, the first input terminal being coupled to the output terminal of the third address latch to receive the stored third external column address, and the second input terminal being coupled to the output terminal of the third address latch through an inverter to receive the complement of the stored third external column address, the second multiplexer further including a third input terminal coupled to the burst counter to receive one of the count bits, the second multiplexer having a control input and being operable to couple the first and second input terminals to respective first and second output terminals responsive to a first state of the control signal, and to couple the third input terminal to one of the first and second output terminals responsive to a second state of the control signal;
• a third multiplexer having first and second input terminals coupled to the first and second output terminals of the first multiplexer, the third multiplexer having a control input and being operable to couple the first input terminal to an output terminal responsive to a first state of the control signal, and to couple the second input terminal to the output terminal responsive to a second state of the control signal;
• a fourth multiplexer having first and second input terminals coupled to the first and second output terminals of the second multiplexer, the fourth multiplexer having a control input and being operable to couple the first input terminal to an output terminal responsive to a first state of the control signal, and to couple the second input terminal to the output terminal responsive to a second state of the control signal;
• and
• a logic circuit having a first input coupled to the output terminal of the first address latch to receive the stored first external column address and a second input coupled to the output terminal of the second address latch to receive the stored second external column address, the logic circuit having an output terminal coupled to the control input of the third multiplexer and an output coupled to the control input of the fourth multiplexer, the logic circuit being operable to generate first and second states of the control signal as a function of the processing of the stored first and second external column addresses.

A memory device, comprising:

• at least one array of memory cells arranged in rows and columns, each of the rows having a row line and each of the columns having a pair of complementary digit lines;
• a row address circuit coupled to the address bus for activating a row line corresponding to a row address coupled to the row address circuit through the address bus;
• a column address circuit coupled to the address bus for receiving an external column address and for selecting a column of the memory array corresponding to an internal column address;
• and
• a burst controller coupled to the address bus and to the column address circuit, the burst controller comprising:
• a first multiplexer having a first input terminal coupled to the column address circuit to receive a first address bit corresponding to the external column address bit and a second input terminal coupled to receive a second address bit corresponding to a complement of the external column address bit, the multiplexer having a control input and being operable to couple one of the received address bits to an output terminal responsive to a control signal applied to the control input, the output terminal being coupled to the memory array to provide the internal column address;
• and
• a logic circuit processing a third address bit corresponding to the external column address bit, the logic circuit being operable to generate the control signal as a function of the processing of the third control signal, the logic circuit having an output terminal coupled to the control input of the multiplexer to cause the multiplexer to couple one of the received address bits to the output terminal of the multiplexer.

A memory device, comprising:

• at least one array of memory cells arranged in rows and columns, each of the rows having a row line and each of the columns having a pair of complementary digit lines;
• a row address circuit coupled to the address bus for activating a row line corresponding to a row address coupled to the row address circuit through the address bus;
• a column address circuit coupled to the address bus for selecting a column for a memory access that corresponds to a column address coupled to the column address circuit through the address bus;
• and
• a column address circuit coupled to the address bus for receiving an external column address and for selecting a column of the memory array corresponding to an internal column address;
• and
• a burst controller coupled to the address bus and to the column address circuit, the burst controller comprising:
• a first address latch receiving a first external column address, the first address latch being structured to store the first external column address and to couple the stored address to an output terminal;
• a second address latch receiving a second external column address, the second address latch being structured to store the second external column address and to couple the stored address to an output terminal;
• a third address latch receiving a third external column address, the third address latch being structured to store the third external column address and to couple the stored address to an output terminal;
• a burst counter generating a plurality of count bits corresponding to a counted column address;
• a first multiplexer having first and second input terminals, the first input terminal being coupled to the output terminal of the second address latch to receive the stored second external column address, and the second input terminal being coupled to the output terminal of the second address latch through an inverter to receive the complement of the stored second external column address, the first multiplexer further including a third input terminal coupled to the burst counter to receive one of the count bits, the first multiplexer having a control input and being operable to couple the first and second input terminals to respective first and second output terminals responsive to a first state of the control signal, and to couple the third input terminal to one of the first and second output terminals responsive to a second state of the control signal;
• a second multiplexer having first and second input terminals, the first input terminal being coupled to the output terminal of the third address latch to receive the stored third external column address, and the second input terminal being coupled to the output terminal of the third address latch through an inverter to receive the complement of the stored third external column address, the second multiplexer further including a third input terminal coupled to the burst counter to receive one of the count bits, the second multiplexer having a control input and being operable to couple the first and second input terminals to respective first and second output terminals responsive to a first state of the control signal, and to couple the third input terminal to one of the first and second output terminals responsive to a second state of the control signal;
• a third multiplexer having first and second input terminals coupled to the first and second output terminals of the first multiplexer, the third multiplexer having a control input and being operable to couple the first input terminal to an output terminal responsive to a first state of the control signal, and to couple the second input terminal to the output terminal responsive to a second state of the control signal, the output terminal being coupled to the memory array to provide the internal column address;
• a fourth multiplexer having first and second input terminals coupled to the first and second output terminals of the second multiplexer, the fourth multiplexer having a control input and being operable to couple the first input terminal to an output terminal responsive to a first state of the control signal, and to couple the second input terminal to the output terminal responsive to a second state of the control signal, the output terminal being coupled to the memory array to provide the internal column address;
• and
• a logic circuit having a first input coupled to the output terminal of the first address latch to receive the stored first external column address and a second input coupled to the output terminal of the second address latch to receive the stored second external column address, the logic circuit having an output terminal coupled to the control input of the third multiplexer and an output coupled to the control input of the fourth multiplexer, the logic circuit being operable to generate first and second states of the control signal as a function of the processing of the stored first and second external column addresses.

A computer system, comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;
• an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
• and
• a memory device coupled to the processor through the processor bus, the memory device comprising:
• at least one array of memory cells arranged in rows and columns, each of the rows having a row line and each of the columns having a pair of complementary digit lines;
• a row address circuit coupled to the address bus for activating a row line corresponding to a row address coupled to the row address circuit through the address bus;
• a column address circuit coupled to the address bus for receiving an external column address and for selecting a column of the memory array corresponding to an internal column address;
• and
• a burst controller coupled to the address bus and to the column address circuit, the burst controller comprising:
• a first multiplexer having a first input terminal coupled to the column address circuit to receive a first address bit corresponding to the external column address bit and a second input terminal coupled to receive a second address bit corresponding to a complement of the external column address bit, the multiplexer having a control input and being operable to couple one of the received address bits to an output terminal responsive to a control signal applied to the control input, the output terminal being coupled to the memory array to provide the internal column address;
• and
• a logic circuit processing a third address bit corresponding to the external column address bit, the logic circuit being operable to generate the control signal as a function of the processing of the third control signal, the logic circuit having an output terminal coupled to the control input of the multiplexer to cause the multiplexer to couple one of the received address bits to the output terminal of the multiplexer.

A method of generating a bit of an internal column address corresponding to an external column address, the method comprising:

• coupling a bit of the external column address and its complement to a selection circuit through a first signal path;
• while the external column address bit and its complement are being coupled through the first signal path, processing the external column address bit to determine the relationship between the internal column address bit and the external column address bit, and generating a control signal corresponding to the determined relationship;
• and
• coupling the control signal to the selection circuit to cause the selection circuit to select either the bit of the external column address or its complement as the internal column address bit based on the control signal.

A method of generating a bit of an internal column address corresponding to an external column address, the method comprising:

• processing the external column address bit to determine the relationship between the internal column address bit and the external column address bit;
• coupling a bit of the external column address and its complement to a selection circuit through a first signal path while the external column address bit is being processed;
• and
• causing the selection circuit to select either the bit of the external column address or its complement as the internal column address bit based on the processing of the external column address bit.