Apparatus and method to improve performance of reads from and writes to shared memory locations
AssigneeInternational Business Machines Corporation
InventorsDonald Lee Freerksen, Sheldon Bernard Levenstein, Gary Michael Lippert
Life of this patent
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Abstract
According to the present invention, an apparatus and method for improving reads from and writes to shared memory locations is disclosed. By giving writes priority over reads, the current invention can decrease the time associated with certain sequences of reads from and writes to shared memory locations. In particular, load-invalidate-load sequences are changed to load—load sequences with the current invention. Furthermore, contention for a shared memory location will be reduced in particular situations when using the current invention.
Claims27
A method for controlling direct accesses by at controller to shared memory locations in a computer system during Limes of address conflict, the computer system comprising a plurality of processors, a plurality of caches, a plurality of bus controllers, and at least one main memory comprising a plurality of memory locations, the method comprising the steps of:
- providing a write list comprising a plurality of writes, each write corresponding to one of the plurality of memory locations;
- providing a first controller of the plurality of bus controllers that is coupled to a first processor of the plurality of processors and to a first cache of the plurality of caches, the first bus controller able to enter a priority mode for each of the writes in the write list;
- receiving a direct read request by the controller to read from a memory location of the plurality of memory locations;
- determining if the memory location is shared;
- accessing the write list to determine, if the memory location is shared, if there is a write that is scheduled to a cache line associated with the first cache and corresponding to the memory location;
- determining if the write corresponding to the memory location is in the priority mode;
- and
- rejecting the direct read request by the controller by issuing a retry command to the controller if there is the write scheduled for the memory location and the write is in the priority state;
- requesting to perform the write to the cache line that corresponds to the memory location;
- and
- entering the priority mode for the write if the request to perform the write is rejected.
A system, comprising a bus controller for controlling direct accesses by at least one other controller to shared memory locations, the bus controller coupled to a bus and the bus coupled to a main memory, the main memory comprising a plurality of memory locations, the bus controller rejecting direct read accesses by the at least one other controller to a first memory location of the plurality of memory locations during times of address conflict by issuing a retry command to the at least one other controller when the bus controller is in a priority mode for a first write that corresponds to the first memory location, wherein the bus controller enters the priority mode for the first write when a request to perform the first write has been rejected.
A system, comprising a bus controller for controlling direct accesses by at least one other controller to shared memory locations, the bus controller coupled to a bus and the bus coupled to a main memory, the main memory comprising a plurality of memory locations, the bus controller rejecting direct read accesses by the at least one other controller to a first memory location of the plurality of memory locations during times of address conflict by issuing a retry command to the at least one oilier controller when the bus controller is in a priority mode for a first write that corresponds to the first memory location, wherein the bus controller comprises a write list that comprises at least one write, each of the at least one write corresponding to a second memory location of the plurality of memory locations, wherein each of the at least one write may be in a priority mode such that the bus controller will reject direct read accesses by a second controller to a second memory location when the bus controller is in a priority mode for a second write in the write list that corresponds to the second memory location.
A computer system comprising:
- a) at least one main memory that comprises a plurality of memory locations for containing data, the at least one main memory coupled to a bus;
- b) at least one processor coupled to the bus;
- c) at least one cache memory coupled to the bus, the at least one cache memory comprising a plurality of cache lines for containing data, each cache line able to be in one of a plurality of states, wherein a shared stale is one of the plurality of states;
- d) at least one bus controller that is coupled to the bus, the at least one bus controller for controlling direct accesses by the at least one processor to and from the bus and for rejecting and allowing read and write accesses by at least one other controller to cache lines of the plurality of cache lines that are in the shared suite and that contain copies of data from memory locations of the plurality of memory locations, the at least one bus controller comprising a write list that is able to contain a plurality of writes, the at least one bus controller able to be in a priority mode for each of the plurality of writes such that the at least one bus controller will reject direct read accesses by the at least one other controller to the memory locations during times of address conflict by issuing a retry command to the at least one other controller if a cache line corresponding to a memory location of the plurality of memory locations is in the shared state when the at least one bus controller is in the priority mode for a write of the plurality of writes and the write corresponds to the memory location;
- and
- e) wherein the cache line contains data from the memory location, and wherein the at least one bus controller for the at least one processor rejects direct read accesses by the at least one other controller to the memory location during times of address conflict by issuing a retry command to the at least one oilier controller when the at least one bus controller for the at least one processor is in the priority mode for the write.
A method for controlling direct accesses by a controller to shared memory locations during times of address conflict in a computer system, the method comprising the steps of:
- receiving a direct read request by the controller to read from a memory location;
- determining if the memory location is shared;
- determining, if the memory location is shared, if there is a write that is scheduled for the memory location arid that is in a priority mode;
- and
- rejecting the direct read request by the controller by issuing a retry command to the controller if there is the write scheduled for the memory location and in the priority state,
- requesting to perform the write to a copy of die memory location;
- and
- entering the priority mode for the write if the request to perform the write is rejected.
Dependencies are inferred from the claim text.