Cache with dynamic control of sub-block fetching
AssigneeWisconsin Alumni Research Foundation
InventorsDouglas C. Burger, David A. Wood
Life of this patent
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Abstract
A cache structure for computer architecture evaluates the subblocks actually used in the cache to modify the granularity of subsequent refreshes of the cache. When many subblocks are used, then subsequent fetches will load the entire block. If only a few subblocks are used, subsequent fetches will fetch only a single subblock. Discontinuous subblock fetching is provided for in a second embodiment in which an entire block is fetched if there is no correlation in the pattern of the subblock usage over time whereas a pattern of discontinuous subblocks is fetched if an historical pattern is revealed. A combination of these two embodiments may also be used.
Claims14
A cache structure for a computer having a processor and associated memory, the cache structure comprising:
- a cache communicating with the memory for loading data therefrom and communicating with the processor for providing data thereto, the cache divided into blocks each holding data from the memory associated with different address ranges of the memory, each block divided into subblocks;
- miss processing circuitry responding to a request from the processor for data of a given subblock not in the cache by loading a variable number of subblocks into the cache, including those not currently requested by the processor, as determined by a fetch size value;
- tag memory having entries indicating which subblocks have been loaded into the cache;
- a subblock use table having entries indicating which subblocks loaded by the miss processing circuitry but not holding data requested by the processor at the time of their loading have had their data provided to the processor after the subblocks were loaded;
- and
- a fetch size controller providing the fetch size value based on the subblock use table.
A cache structure for a computer having a processor and associated memory, the cache structure comprising:
- a cache communicating with the memory for loading data therefrom and communicating with the processor for providing data thereto, the cache divided into blocks holding data from the memory associated with different address ranges of the memory, each block divided into subblocks;
- miss processing circuitry responding to a request from the processor for data of a given address range not in the cache by loading into the cache a variable number of subblocks, including those not in the request, by the processor according to a fetch pattern;
- tag memory having entries indicating which subblocks have been loaded into the cache;
- a subblock use table having at least one entry indicating which of the subblocks loaded by the miss processing circuitry but not holding data requested by the processor at the time of their loading have had their data provided to the processor after the subblock was loaded;
- a fetch pattern controller analyzing patterns of subblock use indicated by the subblock use table to provide the fetch pattern.
Dependencies are inferred from the claim text.