US 6,557,078 B1 · Cache chain structure to implement high bandwidth low latency cache memory subsystem

Abstract

The inventive cache uses a queuing structure which provides out-of-order cache memory access support for multiple accesses, as well as support for managing bank conflicts and address conflicts. The inventive cache can support four data accesses that are hits per clocks, support one access that misses the L1 cache every clock, and support one instruction access every clock. The responses are interspersed in the pipeline, so that conflicts in the queue are minimized. Non-conflicting accesses are not inhibited, however, conflicting accesses are held up until the conflict clears. The inventive cache provides out-of-order support after the retirement stage of a pipeline.

Claims25

Dependent claims

A computer system comprising:

a processor that executes instructions;
and
a multi-level cache structure accessible by said processor to satisfy memory access requests, wherein said multi-level cache structure is configured to receive multiple memory access requests, process the multiple requests in parallel to determine whether one of said multiple levels is capable of satisfying the multiple received memory access requests;
wherein one level of the multi-level cache structure comprises:
tag access logic that compares the addresses of each access request with tags of information stored in the one level to determine whether there is a match;
a queue for holding entries of address information for accesses that have been operated on by the tag access logic;
and
conflict logic for checking each access request with the entries of the queue for conflicts prior to insertion of each access request into the queue.

5 more elements

A method of accessing a multi-level cache of a computer system, the method comprising the steps of:

receiving multiple memory access requests into a multi-level cache structure;
processing the multiple requests in parallel to determine whether one of said multiple levels is capable of satisfying the multiple received memory access requests, and
if determined that at least one the memory access requests can be satisfied by a level of the multi-level cache structure, then satisfying the one memory access request by the level of the multi-level cache structure;
comparing the addresses of each request with tags of information stored in the cache structure to determine whether there is a match with tag access logic;
holding address information for accesses that have been processed by the step of comparing in a queue;
checking each access request with the entries of the queue for conflicts prior to insertion of each access request into the queue with conflict logic.

3 more elements

A computer system comprising:

a processor that executes instructions;
means for receiving multiple memory access requests into a multi-level cache structure;
means for processing the multiple requests in parallel to determine whether one of said multiple levels is capable of satisfying the multiple received memory access requests, and if determined that at least one of the memory access requests can be satisfied by a level of the multi-level cache structure, then satisfying the one memory access request by the level of the multi-level cache structure;
means for comparing the addresses of each request with tags of information stored in the cache structure to determine whether there is a match;
a queue for holding address information for accesses that have been operated on by the means for comparing;
and
means for checking each access request with the entries of the queue for conflicts prior to insertion of each access request into the queue.

4 more elements

Dependencies are inferred from the claim text.

Cache chain structure to implement high bandwidth low latency cache memory subsystem

Life of this patent

Cache chain structure to implement high bandwidth low latency cache memory subsystem

Life of this patent

Abstract

Claims25