US 6,557,068 B2 · High speed peripheral interconnect apparatus, method and system

Abstract

A high speed connection apparatus, method, and system is provided for peripheral components on digital computer systems. The peripheral component interconnect (PCI) specification is used as a baseline for an extended set of commands and attributes. The extended command and the attribute are issued on the bus during the clock cycle immediately after the clock cycle when the initial command was issued. The extended commands and attributes utilize the standard pin connections of conventional PCI devices and buses making the present invention backward-compatible with existing (conventional) PCI devices and legacy computer systems. The conventional PCI command encoding is modified and the extended command is used to qualify the type of transaction and the attributes being used by the initiator of the transaction. The extended commands are divided into four groups based upon the transaction type and the extended command type. Transactions are either byte count or byte-enable transaction types. Extended command types are either validated or immediate. Some extended command encodings are reserved but can be assigned in the future to new extended commands that will behave predictable with current devices.

Claims9

Dependent claims

A method of issuing commands and attributes in a computer system comprising a processor on a first bus, a random access memory on a second bus, a third bus implementing a Peripheral Component Interface protocol, operating on a series of clock cycles, and capable of implementing bus arbitration rules and bus width rules according to a registered Peripheral Component Interface protocol, a core logic chipset bridging the first, second, and third buses, and a PCI device on the third bus, said method comprising:

providing a first portion of the third bus;
issuing a first command on the first portion of the third bus on a first clock cycle of the third bus;
on a second clock cycle immediately after the first clock cycle, issuing a second command on the first portion of the third bus;
providing a second portion of the third bus;
contemporaneous with the issuing of the second command, issuing an attribute on the second portion of the third bus.

2 more elements

A computing system, comprising:

a first bus;
a processor on the first bus;
a second bus;
a random access memory on the second bus;
a third bus implementing a Peripheral Component Interface-based protocol, capable of implementing Registered Peripheral Component Interface arbitration and bus width rules, and operating on a series of clock cycles,
a core logic chipset bridging the first, second buses, and third buses;
a Registered Peripheral Component Interface device on the third bus, the Registered Peripheral Component Interface device implementing the Registered Peripheral Component Interface protocol, capable of issuing a first command on a first clock cycle of the third bus according to the Registered Peripheral Component Interface protocol, capable of issuing an extended command of the first command on a second clock cycle of the third bus according the Registered Peripheral Component Interface protocol, and capable of issuing an attribute during the second clock cycle.

4 more elements

Dependencies are inferred from the claim text.

High speed peripheral interconnect apparatus, method and system

Life of this patent

High speed peripheral interconnect apparatus, method and system

Life of this patent

Abstract

Claims9